专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08867282B2 Semiconductor apparatus with open bit line structure 有权
标题翻译：具有开放位线结构的半导体装置
公开(公告)号：US08867282B2
公开(公告)日：2014-10-21
申请号：US13339183
申请日：2011-12-28
申请人： Tae Sik Yun , Kee Teok Park
发明人： Tae Sik Yun , Kee Teok Park
IPC分类号： G11C7/00 , G11C29/00 , G11C29/24 , G11C11/4099 , G11C29/12 , G11C11/401
CPC分类号： G11C11/4099 , G11C11/401 , G11C29/24 , G11C2029/1202
摘要： A semiconductor apparatus with an open bit line structure includes a memory bank including a plurality of memory cell blocks and dummy mats, in which a plurality of bit lines are formed, a bit line sense amplifier configured to be arranged between the plurality of memory cell blocks and the dummy mats, compare a voltage difference between a bit line and a complementary bit line, and amplify the difference, and a dummy word line driving unit configured to selectively activate a dummy word line of the dummy mat in response to a test mode.
摘要翻译：具有开放位线结构的半导体装置包括：存储体，包括多个存储单元块和形成有多个位线的虚拟垫;配置为布置在多个存储单元块之间的位线读出放大器和虚拟垫，比较位线和互补位线之间的电压差，并放大差值;虚拟字线驱动单元，被配置为响应于测试模式选择性地激活虚拟垫的虚拟字线。

2. 发明授权

US08553478B2 Semiconductor integrated circuit and control method thereof 有权
标题翻译：半导体集成电路及其控制方法
公开(公告)号：US08553478B2
公开(公告)日：2013-10-08
申请号：US13190169
申请日：2011-07-25
申请人： Tae Sik Yun , Kang Seol Lee
发明人： Tae Sik Yun , Kang Seol Lee
IPC分类号： G11C7/00
CPC分类号： G11C29/883 , G11C5/04 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a first chip and a second chip stacked together with the first chip. A first memory area is formed on the second chip, and a second memory area for repairing a failure of the first memory area is formed on the first chip.
摘要翻译：半导体集成电路包括与第一芯片堆叠在一起的第一芯片和第二芯片。在第二芯片上形成第一存储区域，并且在第一芯片上形成用于修复第一存储区域的故障的第二存储区域。

3. 发明申请

US20130049833A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20130049833A1
公开(公告)日：2013-02-28
申请号：US13445761
申请日：2012-04-12
申请人： Sang Jin BYEON , Tae Sik YUN
发明人： Sang Jin BYEON , Tae Sik YUN
IPC分类号： H03L7/00 , H03K3/017
CPC分类号： H03K5/06 , G06F1/12 , H03K5/08
摘要： A semiconductor apparatus is provided. The apparatus includes a transmission control unit configured to generate, in response to a received pulse signal having a first pulse width, transmission control signals with a second pulse width larger than the first pulse width and synchronization control signals with a third pulse width larger than the second pulse width. The apparatus also includes a reception control unit configured to generate reception control signals in response to the synchronization control signals.
摘要翻译：提供一种半导体装置。该装置包括：传输控制单元，被配置为响应于具有第一脉冲宽度的接收脉冲信号，生成具有大于第一脉冲宽度的第二脉冲宽度的传输控制信号和具有大于第一脉冲宽度的第三脉冲宽度的同步控制信号第二脉冲宽度。该装置还包括：接收控制单元，被配置为响应于同步控制信号产生接收控制信号。

4. 发明授权

US08339872B2 Semiconductor memory apparatus and method of driving bit-line sense amplifier 有权
标题翻译：驱动位线读出放大器的半导体存储装置及方法
公开(公告)号：US08339872B2
公开(公告)日：2012-12-25
申请号：US12648983
申请日：2009-12-29
申请人： Tae-Sik Yun , Jae-Jin Lee
发明人： Tae-Sik Yun , Jae-Jin Lee
IPC分类号： G11C7/00 , G11C7/02 , G11C5/14
CPC分类号： G11C11/4091 , G11C5/147
摘要： Disclosed is a semiconductor memory apparatus which improves the time to transmit write data to a memory cell and improves data retention time of the memory cell. To this end, the semiconductor memory apparatus includes a bit-line sense amplifier that senses and amplifies data of bit-line pairs by driving power supplied through a pull up power line and a pull down power line and transmits the amplified data to a memory cell. A bit-line sense amplification power supply unit supplies pull up driving voltage and pull down driving voltage to the pull up and pull down power lines in an active mode and supplies an over driving voltage and the pull down driving voltage having a higher voltage level than the pull up driving voltage to the pull up and pull down power lines until the memory cell is deactivated in a precharge mode.
摘要翻译：公开了一种半导体存储装置，其改善了将数据写入存储单元的时间，并且提高了存储单元的数据保持时间。为此，半导体存储装置包括：位线读出放大器，其通过驱动通过上拉电力线和下拉电力线提供的电力来感测和放大位线对的数据，并将放大的数据发送到存储单元。位线检测放大电源单元提供上拉驱动电压并将驱动电压下拉至上拉电源线并将其下拉至主动模式，并提供过驱动电压和下拉驱动电压，具有比上拉驱动电压上拉并下拉电源线，直到存储单元在预充电模式下被禁用。

5. 发明授权

US08248096B2 Test mode signal generating device 有权
标题翻译：测试模式信号发生装置
公开(公告)号：US08248096B2
公开(公告)日：2012-08-21
申请号：US12637198
申请日：2009-12-14
申请人： Tae Sik Yun
发明人： Tae Sik Yun
IPC分类号： G01R31/02
CPC分类号： G01R31/31701
摘要： Various embodiments of a test mode signal generating device are disclosed. The device includes first and second test mode signal generating units. The first test mode signal generating unit is configured to receive test address signals to generate a first test mode signal when a first mode conversion signal is enabled. The first test mode signal generating unit is also configured to enable a second mode conversion signal when the test address signals correspond to a first predetermined combination. The second test mode signal generating unit is configured to receive the test address signals to generate a second test mode signal when the second mode conversion signal is enabled. The second test mode signal generating unit is also configured to enable the first mode conversion signal when the test address signals correspond to a second predetermined combination.
摘要翻译：公开了测试模式信号产生装置的各种实施例。该装置包括第一和第二测试模式信号产生单元。第一测试模式信号产生单元被配置为当启用第一模式转换信号时接收测试地址信号以产生第一测试模式信号。第一测试模式信号产生单元还被配置为当测试地址信号对应于第一预定组合时启用第二模式转换信号。第二测试模式信号产生单元被配置为当第二模式转换信号被使能时，接收测试地址信号以产生第二测试模式信号。第二测试模式信号产生单元还被配置为当测试地址信号对应于第二预定组合时启用第一模式转换信号。

6. 发明授权

US08213251B2 Semiconductor memory device and method for driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US08213251B2
公开(公告)日：2012-07-03
申请号：US12829987
申请日：2010-07-02
申请人： Tae-Sik Yun , Kang-Seol Lee
发明人： Tae-Sik Yun , Kang-Seol Lee
IPC分类号： G11C7/02
CPC分类号： G11C11/4091 , G11C7/08 , G11C7/1048 , G11C11/4087 , G11C2207/005
摘要： A semiconductor memory device includes a cell block including a first bit line, a sense amplifier unit including a second bit line and configured to amplify a data signal applied to the second bit line, a connection unit configured to selectively connect the first bit line and the second bit line, a connection control unit configured to receive a control signal for driving the sense amplifier unit and a selection signal for selecting the cell block and generate a connection signal for activating the connection unit at a first time, and a sense amplifier driving control unit configured to receive the control signal and generate a sense amplifier driving signal for driving the sense amplifier unit at a second time after the first time.
摘要翻译：半导体存储器件包括：包括第一位线的单元块，包括第二位线的读出放大器单元，用于放大施加到第二位线的数据信号;连接单元，被配置为选择性地将第一位线和第二位线，连接控制单元，被配置为接收用于驱动读出放大器单元的控制信号和用于选择单元块的选择信号，并且在第一时间产生用于激活连接单元的连接信号，以及读出放大器驱动控制被配置为接收控制信号并且在第一次之后的第二时间产生用于驱动读出放大器单元的读出放大器驱动信号。

7. 发明申请

US20120119764A1 TEST MODE CONTROL CIRCUIT OF SEMICONDUCTOR APPARATUS AND CONTROL METHOD THEREOF 有权
标题翻译：半导体器件的测试模式控制电路及其控制方法
公开(公告)号：US20120119764A1
公开(公告)日：2012-05-17
申请号：US13181921
申请日：2011-07-13
申请人： Tae Sik YUN , Jong Chern LEE
发明人： Tae Sik YUN , Jong Chern LEE
IPC分类号： G01R31/00
CPC分类号： G01R31/31724 , G11C29/14 , G11C29/46 , G11C29/78 , G11C29/802
摘要： Various embodiments of a test mode control circuit of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, the test mode control circuit may include: a test mode control block configured to generate a plurality of control signal sets in response to a first address signal set and a second address signal set which are sequentially inputted; a test mode transfer block configured to transfer a plurality of test mode signals, which are generated according to a combination of the plurality of control signal sets, to a plurality of circuit blocks of the semiconductor apparatus; and a plurality of global lines configured to transmit the plurality of control signal sets to the test mode transfer block.
摘要翻译：公开了半导体装置的测试模式控制电路的各种实施例及相关方法。在一个示例性实施例中，测试模式控制电路可以包括：测试模式控制块，被配置为响应于顺序地输入的第一地址信号组和第二地址信号组而产生多个控制信号集; 测试模式传送块，被配置为将根据所述多个控制信号组的组合产生的多个测试模式信号传送到所述半导体装置的多个电路块; 以及配置成将多个控制信号组发送到测试模式传送块的多个全局线。

8. 发明授权

US07969800B2 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US07969800B2
公开(公告)日：2011-06-28
申请号：US12493734
申请日：2009-06-29
申请人： Tae Sik Yun , Kang Seol Lee
发明人： Tae Sik Yun , Kang Seol Lee
IPC分类号： G11C7/00
CPC分类号： G11C8/18
摘要： A semiconductor memory apparatus includes a row path activating unit configured to generate a line connection control signal according to a received address and active command. The semiconductor memory apparatus also includes a cell array circuit unit including an input/output line switch for connecting a first input/output line in a cell block and a second input/output line extending to the outside of the cell block. The cell array also including a bit line switch for connecting a bit line pair to each other. The input/output line switch and the bit line switch are further controlled by the line connection control signal from the row path activating unit.
摘要翻译：一种半导体存储装置，包括：行路径激活部，被配置为根据接收到的地址和主动命令生成线路连接控制信号。半导体存储装置还包括一个单元阵列电路单元，包括用于连接单元块中的第一输入/输出线和延伸到单元块外部的第二输入/输出线的输入/输出线开关。单元阵列还包括用于将位线对彼此连接的位线开关。输入/输出线路开关和位线开关进一步由来自行路径激活单元的线路连接控制信号控制。

9. 发明申请

US20110075491A1 SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF DRIVING BIT-LINE SENSE AMPLIFIER 有权
标题翻译：半导体存储器装置和驱动位线检测放大器的方法
公开(公告)号：US20110075491A1
公开(公告)日：2011-03-31
申请号：US12648983
申请日：2009-12-29
申请人： Tae-Sik Yun , Jae-Jin Lee
发明人： Tae-Sik Yun , Jae-Jin Lee
IPC分类号： G11C7/00 , G11C7/02 , G11C5/14
CPC分类号： G11C11/4091 , G11C5/147
摘要： Disclosed is a semiconductor memory apparatus which improves the time to transmit write data to a memory cell and improves data retention time of the memory cell. To this end, the semiconductor memory apparatus includes a bit-line sense amplifier that senses and amplifies data of bit-line pairs by driving power supplied through a pull up power line and a pull down power line and transmits the amplified data to a memory cell. A bit-line sense amplification power supply unit supplies pull up driving voltage and pull down driving voltage to the pull up and pull down power lines in an active mode and supplies an over driving voltage and the pull down driving voltage having a higher voltage level than the pull up driving voltage to the pull up and pull down power lines until the memory cell is deactivated in a precharge mode.
摘要翻译：公开了一种半导体存储装置，其改善了将数据写入存储单元的时间，并且提高了存储单元的数据保持时间。为此，半导体存储装置包括：位线读出放大器，其通过驱动通过上拉电力线和下拉电力线提供的电力来感测和放大位线对的数据，并将放大的数据发送到存储单元。位线检测放大电源单元提供上拉驱动电压并将驱动电压下拉至上拉电源线并将其下拉至主动模式，并提供过驱动电压和下拉驱动电压，具有比上拉驱动电压上拉并下拉电源线，直到存储单元在预充电模式下被禁用。

10. 发明申请

US20110025364A1 Test Mode Signal Generating Device 有权
标题翻译：测试模式信号发生装置
公开(公告)号：US20110025364A1
公开(公告)日：2011-02-03
申请号：US12637198
申请日：2009-12-14
申请人： Tae Sik YUN
发明人： Tae Sik YUN
IPC分类号： G01R31/26 , G06F11/00
CPC分类号： G01R31/31701
摘要： Various embodiments of a test mode signal generating device are disclosed. The device includes first and second test mode signal generating units. The first test mode signal generating unit is configured to receive test address signals to generate a first test mode signal when a first mode conversion signal is enabled. The first test mode signal generating unit is also configured to enable a second mode conversion signal when the test address signals correspond to a first predetermined combination. The second test mode signal generating unit is configured to receive the test address signals to generate a second test mode signal when the second mode conversion signal is enabled. The second test mode signal generating unit is also configured to enable the first mode conversion signal when the test address signals correspond to a second predetermined combination.
摘要翻译：公开了测试模式信号产生装置的各种实施例。该装置包括第一和第二测试模式信号发生单元。第一测试模式信号产生单元被配置为当启用第一模式转换信号时接收测试地址信号以产生第一测试模式信号。第一测试模式信号产生单元还被配置为当测试地址信号对应于第一预定组合时启用第二模式转换信号。第二测试模式信号产生单元被配置为当第二模式转换信号被使能时，接收测试地址信号以产生第二测试模式信号。第二测试模式信号产生单元还被配置为当测试地址信号对应于第二预定组合时使能第一模式转换信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式