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161. 发明申请

US20110108900A1 BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR 有权
标题翻译：双向自对准FET电容器
公开(公告)号：US20110108900A1
公开(公告)日：2011-05-12
申请号：US12616861
申请日：2009-11-12
申请人： Leland Chang , Chung-Hsun Lin , Brian L. Ji , Jeffrey W. Sleight
发明人： Leland Chang , Chung-Hsun Lin , Brian L. Ji , Jeffrey W. Sleight
IPC分类号： H01L29/94 , H01L21/334
CPC分类号： H01L27/0811 , H01L21/26586 , H01L21/823418 , H01L21/84 , H01L27/1203 , H01L29/66181 , H01L29/94
摘要： A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack.
摘要翻译：形成场效应晶体管（FET）电容器的方法包括：形成沟道区; 在沟道区上形成栅叠层; 在所述栅极堆叠的第一侧上形成第一延伸区域，所述第一延伸区域通过以第一角度注入第一掺杂材料形成，使得阴极区域存在于所述栅极叠层的第二侧上; 以及在所述栅极堆叠的第二侧上形成第二延伸区域，所述第二延伸区域通过以第二角度注入第二掺杂材料形成，使得阴极区域存在于所述栅极叠层的第一侧上。

162. 发明申请

US20110049626A1 ASYMMETRIC EMBEDDED SILICON GERMANIUM FIELD EFFECT TRANSISTOR 有权
标题翻译：不对称嵌入硅锗电场效应晶体管
公开(公告)号：US20110049626A1
公开(公告)日：2011-03-03
申请号：US12551804
申请日：2009-09-01
申请人： CHUNG-HSUN LIN , Isaac Lauer , Jeffrey W. Sleight
发明人： CHUNG-HSUN LIN , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78687 , H01L21/26586 , H01L29/6656 , H01L29/66636 , H01L29/66659 , H01L29/66742 , H01L29/7835 , H01L29/78612 , H01L29/78624
摘要： A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source region that includes embedded silicon germanium is formed within the semiconductor layer. A drain region that includes embedded silicon germanium is formed within the semiconductor layer. The source region includes an angled implantation region that extends into the embedded silicon germanium of the source region, and is asymmetric relative to the drain region.
摘要翻译：公开了一种半导体器件，集成电路及其制造方法。半导体器件包括形成在绝缘体上硅衬底的有源区上的栅叠层。在栅极堆叠上形成栅极间隔物。在半导体层内形成包括嵌入硅锗的源区。在半导体层内形成包括嵌入硅锗的漏区。源极区域包括延伸到源极区域的嵌入式硅锗中的成角度的注入区域，并且相对于漏极区域是不对称的。

163. 发明授权

US07879650B2 Method of providing protection against charging damage in hybrid orientation transistors 有权
标题翻译：在混合取向晶体管中提供防止充电损坏的方法
公开(公告)号：US07879650B2
公开(公告)日：2011-02-01
申请号：US12002807
申请日：2007-12-19
申请人： Terence B. Hook , Anda C. Mocuta , Jeffrey W. Sleight , Anthony K. Stamper
发明人： Terence B. Hook , Anda C. Mocuta , Jeffrey W. Sleight , Anthony K. Stamper
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/0251 , H01L27/0629 , H01L27/1203 , H01L27/1207
摘要： In a method of fabricating a CMOS structure, a bulk device can be formed in a first region in conductive communication with an underlying bulk region of the substrate. A first gate conductor may overlie the first region. An SOI device can be formed which has a source drain conduction path in a SOI layer, i.e., a semiconductor layer that is separated from the bulk region by a buried dielectric region. The crystal orientations of the SOI layer and the bulk region can be different. A first diode can be formed in a second region of the substrate in conductive communication with the bulk region. The first diode may be connected in a reverse-biased orientation to a first gate conductor above the SOI layer, such that a voltage on the gate conductor that exceeds the breakdown voltage can be discharged through the first diode to the bulk region of the substrate. A second diode may be formed in a third region of the substrate in conductive communication with the bulk region. The second diode may be connected in a reverse-biased orientation to a source region or a drain region of an NFET.
摘要翻译：在制造CMOS结构的方法中，本体器件可以形成在与衬底的下面的主体区域导电连通的第一区域中。第一栅极导体可以覆盖在第一区域上。可以形成在SOI层中具有源极漏极传导路径的SOI器件，即通过掩埋电介质区域与本体区域分离的半导体层。 SOI层和体区的晶体取向可以不同。第一二极管可以形成在衬底的与体区导电连通的第二区域中。第一二极管可以以反向偏置的方式连接到SOI层上方的第一栅极导体，使得超过击穿电压的栅极导体上的电压可以通过第一二极管放电到衬底的主体区域。第二二极管可以形成在衬底的与体区导电连通的第三区域中。第二二极管可以以反向偏置的方式连接到NFET的源极区域或漏极区域。

164. 发明申请

US20110012202A1 Selective Floating Body SRAM Cell 有权
公开(公告)号：US20110012202A1
公开(公告)日：2011-01-20
申请号：US12505824
申请日：2009-07-20
申请人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/088 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/1207 , H01L27/1211 , H01L29/7841
摘要： A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.

165. 发明授权

US07826251B2 High performance metal gate polygate 8 transistor SRAM cell with reduced variability 有权
标题翻译：高性能金属门Polygate 8晶体管SRAM单元具有降低的变异性
公开(公告)号：US07826251B2
公开(公告)日：2010-11-02
申请号：US12125637
申请日：2008-05-22
申请人： Leland Chang , Jeffrey W. Sleight
发明人： Leland Chang , Jeffrey W. Sleight
IPC分类号： G11C11/00
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/0207 , Y10S257/903
摘要： A static random access memory cell includes a metal hi-k layer; a poly-SiON gate stack over the metal hi-k layer; a plurality of inverters disposed within the poly-SiON gate stack; and a plurality of field effect transistors placed in the metal hi-k layer.
摘要翻译：静态随机存取存储单元包括金属hi-k层; 金属hi-k层上的多晶硅栅叠层; 设置在所述多晶硅栅极叠层内的多个反相器; 以及放置在金属hi-k层中的多个场效应晶体管。

166. 发明申请

US20100224940A1 Partially and Fully Silicided Gate Stacks 有权
标题翻译：部分和全硅酸盐堆叠
公开(公告)号：US20100224940A1
公开(公告)日：2010-09-09
申请号：US12782388
申请日：2010-05-18
申请人： Leland Chang , Renee Tong Mo , Jeffrey W. Sleight
发明人： Leland Chang , Renee Tong Mo , Jeffrey W. Sleight
IPC分类号： H01L27/092
CPC分类号： H01L21/823835 , H01L21/28052 , H01L21/28097 , H01L21/823842 , H01L29/4933 , H01L29/4975
摘要： Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal gate layer; a first NFET gate stack silicon layer over the NFET gate stack metal gate layer; a second NFET gate stack silicon layer over a side of the first NFET gate stack silicon layer opposite the NFET gate stack metal gate layer, wherein an interface is defined between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer; and an NFET gate stack silicide region that extends through the interface between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer.
摘要翻译：提供了金属氧化物半导体（MOS）器件及其制造技术。一方面，提供一种金属氧化物半导体器件，其包括：衬底; 以及至少一个在衬底上具有栅极堆叠的n沟道场效应晶体管（NFET）。 NFET栅极堆叠包括NFET栅极叠层金属栅极层; 在NFET栅极堆叠金属栅极层上的第一NFET栅极叠层硅层; 在所述第一NFET栅极叠层硅层的与所述NFET栅极堆叠金属栅极层相对的一侧上的第二NFET栅极堆叠硅层，其中在所述第一NFET栅极堆叠硅层和所述第二NFET栅极堆叠硅层之间限定界面; 以及延伸穿过第一NFET栅极堆叠硅层和第二NFET栅极堆叠硅层之间的界面的NFET栅极堆叠硅化物区域。

167. 发明授权

US07713807B2 High-performance CMOS SOI devices on hybrid crystal-oriented substrates 失效
标题翻译：高性能CMOS SOI器件在混合晶体取向衬底上
公开(公告)号：US07713807B2
公开(公告)日：2010-05-11
申请号：US11958877
申请日：2007-12-18
申请人： Bruce B. Doris , Kathryn W. Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey W. Sleight , Min Yang
发明人： Bruce B. Doris , Kathryn W. Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey W. Sleight , Min Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/76275 , H01L21/823807 , H01L21/84
摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.
摘要翻译：提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

168. 发明申请

US20090305471A1 THIN SILICON SINGLE DIFFUSION FIELD EFFECT TRANSISTOR FOR ENHANCED DRIVE PERFORMANCE WITH STRESS FILM LINERS 审中-公开
标题翻译：薄硅单晶扩散场效应晶体管，用于增强驱动器性能与应力膜线
公开(公告)号：US20090305471A1
公开(公告)日：2009-12-10
申请号：US12541605
申请日：2009-08-14
申请人： Leland Chang , David M. Fried , John M. Hergenrother , Ghavam Shahidi , Jeffrey W. Sleight
发明人： Leland Chang , David M. Fried , John M. Hergenrother , Ghavam Shahidi , Jeffrey W. Sleight
IPC分类号： H01L21/762 , H01L21/8238 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/458 , H01L29/66772 , H01L29/7843
摘要： The present invention provides a semiconducting device structure including a thin SOI region, wherein the SOI device is formed with an optional single thin diffusion, i.e., offset, spacer and a single diffusion implant. The device silicon thickness is thin enough to permit the diffusion implants to abut the buried insulator but thick enough to form a contacting silicide. Stress layer liner films are used both over nFET and pFET device regions to enhance performance.
摘要翻译：本发明提供了一种包括薄SOI区域的半导体器件结构，其中SOI器件形成有可选的单个薄扩散，即偏移，间隔物和单个扩散注入。器件硅厚度足够薄以允许扩散植入物邻接埋入的绝缘体，但是足够厚以形成接触硅化物。应力层衬垫膜都用于nFET和pFET器件区域，以提高性能。

169. 发明申请

US20090290439A1 HIGH PERFORMANCE METAL GATE POLYGATE 8 TRANSISTOR SRAM CELL WITH REDUCED VARIABILITY 有权
标题翻译：高性能金属门聚合物8晶体管SRAM电池具有降低的可变性
公开(公告)号：US20090290439A1
公开(公告)日：2009-11-26
申请号：US12125637
申请日：2008-05-22
申请人： Leland Chang , Jeffrey W. Sleight
发明人： Leland Chang , Jeffrey W. Sleight
IPC分类号： G11C7/00
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/0207 , Y10S257/903
摘要： A static random access memory cell includes a metal hi-k layer; a poly-SiON gate stack over the metal hi-k layer; a plurality of inverters disposed within the poly-SiON gate stack; and a plurality of field effect transistors placed in the metal hi-k layer.
摘要翻译：静态随机存取存储单元包括金属hi-k层; 金属hi-k层上的多晶硅栅叠层; 设置在所述多晶硅栅极叠层内的多个反相器; 以及放置在金属hi-k层中的多个场效应晶体管。

170. 发明申请

US20090289305A1 ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBEDDED SIGE PFET EXTENSION 审中-公开
标题翻译：具有增加的外延源和漏极和嵌入式信号扩展的超薄SOI CMOS
公开(公告)号：US20090289305A1
公开(公告)日：2009-11-26
申请号：US12535306
申请日：2009-08-04
申请人： Amlan Majumdar , Gen Pei , Zhibin Ren , Dinkar Singh , Jeffrey W. Sleight
发明人： Amlan Majumdar , Gen Pei , Zhibin Ren , Dinkar Singh , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L29/786
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1203 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.
摘要翻译：通过将嵌入的pFET SiGe扩展与升高的源极/漏极区域集成来提高超薄硅上氧化物（UTSOI）FET器件中的沟道载流子迁移率的方法。该方法包括选择性地生长pFET区域中的嵌入式SiGe（eSiGe）扩展，并在CMOS上形成无应力的升高的Si或SiGe源极/漏极（RSD）区域。 eSiGe延伸区增强了pFET通道中的空穴迁移率，并降低了pFET延伸中的电阻。无应变的升高的源极/漏极区域减小了两个UTSOI pFET和nFET中的接触电阻。

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