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1. 发明授权

US07713807B2 High-performance CMOS SOI devices on hybrid crystal-oriented substrates 失效
标题翻译：高性能CMOS SOI器件在混合晶体取向衬底上
公开(公告)号：US07713807B2
公开(公告)日：2010-05-11
申请号：US11958877
申请日：2007-12-18
申请人： Bruce B. Doris , Kathryn W. Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey W. Sleight , Min Yang
发明人： Bruce B. Doris , Kathryn W. Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey W. Sleight , Min Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/76275 , H01L21/823807 , H01L21/84
摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.
摘要翻译：提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

2. 发明授权

US07329923B2 High-performance CMOS devices on hybrid crystal oriented substrates 失效
标题翻译：混合晶体取向基板上的高性能CMOS器件
公开(公告)号：US07329923B2
公开(公告)日：2008-02-12
申请号：US10250241
申请日：2003-06-17
申请人： Bruce B. Doris , Kathryn W. Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey W. Sleight , Min Yang
发明人： Bruce B. Doris , Kathryn W. Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey W. Sleight , Min Yang
IPC分类号： H01L27/01
CPC分类号： H01L21/76275 , H01L21/823807 , H01L21/84
摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.
摘要翻译：提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

3. 发明申请

US20080096330A1 HIGH-PERFORMANCE CMOS SOI DEVICES ON HYBRID CRYSTAL-ORIENTED SUBSTRATES 失效
标题翻译：高性能CMOS SOI器件在混合晶体导向衬底上的应用
公开(公告)号：US20080096330A1
公开(公告)日：2008-04-24
申请号：US11958877
申请日：2007-12-18
申请人： Bruce Doris , Kathryn Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey Sleight , Min Yang
发明人： Bruce Doris , Kathryn Guarini , Meikei Ieong , Shreesh Narasimha , Kern Rim , Jeffrey Sleight , Min Yang
IPC分类号： H01L21/84
CPC分类号： H01L21/76275 , H01L21/823807 , H01L21/84
摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.
摘要翻译：提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

4. 发明申请

US20050236687A1 Strained silicon CMOS on hybrid crystal orientations 失效
标题翻译：应变硅CMOS在混合晶体取向上
公开(公告)号：US20050236687A1
公开(公告)日：2005-10-27
申请号：US10830347
申请日：2004-04-22
申请人： Kevin Chan , Bruce Doris , Kathryn Guarini , Meikei Ieong , Shreesh Narasimha , Alexander Reznicek , Kern Rim , Devendra Sadana , Leathen Shi , Jeffrey Sleight , Min Yang
发明人： Kevin Chan , Bruce Doris , Kathryn Guarini , Meikei Ieong , Shreesh Narasimha , Alexander Reznicek , Kern Rim , Devendra Sadana , Leathen Shi , Jeffrey Sleight , Min Yang
IPC分类号： H01L27/08 , H01L21/02 , H01L21/20 , H01L21/336 , H01L21/762 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/04 , H01L29/76 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
摘要翻译：提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。该方法提供混合基板，其中至少一个器件层包括应变Si。

5. 发明授权

US07187059B2 Compressive SiGe <110> growth and structure of MOSFET devices 有权
标题翻译：压电SiGe <110> MOSFET器件的增长和结构
公开(公告)号：US07187059B2
公开(公告)日：2007-03-06
申请号：US10875727
申请日：2004-06-24
申请人： Kevin K. Chan , Kathryn W. Guarini , Meikel Ieong , Kern Rim , Min Yang
发明人： Kevin K. Chan , Kathryn W. Guarini , Meikel Ieong , Kern Rim , Min Yang
IPC分类号： H01L29/04 , H01L31/036 , H01L29/06 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/045 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02658 , H01L21/823807 , H01L29/1054
摘要： A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600° C. and introducing both a Si containing gas and a Ge containing gas. A method for chemically preparing a substrate for epitaxial deposition is described including the steps of immersing a substrate in a series of baths containing ozone, dilute HF, deionized water, HCL acid and deionized water, respectively, followed by drying the substrate in an inert atmosphere to obtain a substrate surface free of impurities and with a root mean square (RMS) surface roughness of less than 0.1 run.
摘要翻译：描述了用于导电载体的结构和形成方法，其结合了具有在<110>中具有上表面的Si或SiGe的单晶衬底和SiGe的形貌或外延层，其Ge浓度与衬底的Ge不同，由此形成PS形态层正在紧张。描述了一种用于形成半导体外延层的方法，其包括在快速热化学气相沉积（RTCVD）工具中通过将工具中的温度增加到约600℃来形成拟态或外延层的步骤，并引入含Si气体和含Ge的气体。描述了用于化学制备用于外延沉积的衬底的方法，其包括以下步骤：将衬底浸入含有臭氧，稀HF，去离子水，HCL酸和去离子水的一系列浴中，然后在惰性气氛中干燥衬底以获得不含杂质的基体表面，均方根（RMS）的表面粗糙度小于0.1nm。

6. 发明申请

US20080042215A1 STRAINED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) ON ROTATED WAFERS AND METHODS THEREOF 失效
标题翻译：旋转补偿金属氧化物半导体（CMOS）及其方法
公开(公告)号：US20080042215A1
公开(公告)日：2008-02-21
申请号：US11925088
申请日：2007-10-26
申请人： Meikei Ieong , Qiging Ouyang , Kern Rim
发明人： Meikei Ieong , Qiging Ouyang , Kern Rim
IPC分类号： H01L29/94
CPC分类号： H01L21/823807 , H01L27/0922 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.
摘要翻译：本发明提供CMOS结构，其包括位于旋转的半导体衬底上的至少一个应变pFET，以改善器件性能。具体地，本发明利用具有（100）晶体取向的含Si半导体衬底，其中衬底旋转约45°，使得CMOS器件沟道沿<100>方向定位。通过在衬底中形成嵌入的应力阱，或者通过利用嵌入的应力阱的组合，或者通过利用嵌入的应力阱的组合，可以在包括至少pFET和任选的nFET，特别是沟道的CMOS结构上诱导应变，一个紧张的班轮。本发明还提供了制造上述半导体结构的方法。

7. 发明申请

US20060237785A1 Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereof 有权
标题翻译：旋转晶片上的应变互补金属氧化物半导体（CMOS）及其方法
公开(公告)号：US20060237785A1
公开(公告)日：2006-10-26
申请号：US11112820
申请日：2005-04-22
申请人： Meikei Ieong , Qiqing Ouyang , Kern Rim
发明人： Meikei Ieong , Qiqing Ouyang , Kern Rim
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L27/0922 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.
摘要翻译：本发明提供CMOS结构，其包括位于旋转的半导体衬底上的至少一个应变pFET，以改善器件性能。具体地，本发明利用具有（100）晶体取向的含Si半导体衬底，其中衬底旋转约45°，使得CMOS器件沟道沿<100>方向定位。通过在衬底中形成嵌入的应力阱，或者通过利用嵌入的应力阱的组合，或者通过利用嵌入的应力阱的组合，可以在包括至少pFET和任选的nFET，特别是沟道的CMOS结构上诱导应变，一个紧张的班轮。本发明还提供了制造上述半导体结构的方法。

8. 发明授权

US07348611B2 Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereof 有权
标题翻译：旋转晶片上的应变互补金属氧化物半导体（CMOS）及其方法
公开(公告)号：US07348611B2
公开(公告)日：2008-03-25
申请号：US11112820
申请日：2005-04-22
申请人： Meikei Ieong , Qiqing C. Ouyang , Kern Rim
发明人： Meikei Ieong , Qiqing C. Ouyang , Kern Rim
IPC分类号： H01L29/73
CPC分类号： H01L21/823807 , H01L27/0922 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.
摘要翻译：本发明提供CMOS结构，其包括位于旋转的半导体衬底上的至少一个应变pFET，以改善器件性能。具体地，本发明利用具有（100）晶体取向的含Si半导体衬底，其中衬底旋转约45°，使得CMOS器件沟道沿<100>方向定位。通过在衬底中形成嵌入的应力阱，或者通过利用嵌入的应力阱的组合，或者通过利用嵌入的应力阱的组合，可以在包括至少pFET和任选的nFET，特别是沟道的CMOS结构上诱导应变，一个紧张的班轮。本发明还提供了制造上述半导体结构的方法。

9. 发明授权

US07675055B2 Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereof 失效
标题翻译：旋转晶片上的应变互补金属氧化物半导体（CMOS）及其方法
公开(公告)号：US07675055B2
公开(公告)日：2010-03-09
申请号：US11925088
申请日：2007-10-26
申请人： Meikei Ieong , Qiging C. Ouyang , Kern Rim
发明人： Meikei Ieong , Qiging C. Ouyang , Kern Rim
IPC分类号： H01L31/00
CPC分类号： H01L21/823807 , H01L27/0922 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.
摘要翻译：本发明提供CMOS结构，其包括位于旋转的半导体衬底上的至少一个应变pFET，以改善器件性能。具体地，本发明利用具有（100）晶体取向的含Si半导体衬底，其中衬底旋转约45°，使得CMOS器件沟道沿<100>方向定位。通过在衬底中形成嵌入的应力阱，或者通过利用嵌入的应力阱的组合，或者通过利用嵌入的应力阱的组合，可以在包括至少pFET和任选的nFET，特别是沟道的CMOS结构上诱导应变，一个紧张的班轮。本发明还提供了制造上述半导体结构的方法。

10. 发明申请

US20080191243A1 SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE STRUCTURE 失效
标题翻译：半导体结构和形成结构的方法
公开(公告)号：US20080191243A1
公开(公告)日：2008-08-14
申请号：US11672599
申请日：2007-02-08
申请人： Yaocheng Liu , Shreesh Narasimha , Katsunori Onishi , Kern Rim
发明人： Yaocheng Liu , Shreesh Narasimha , Katsunori Onishi , Kern Rim
IPC分类号： H01L27/092 , H01L29/778 , H01L21/8238 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/26506 , H01L21/26513 , H01L21/28247 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/1045 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.
摘要翻译：公开了具有完全包含在非晶化区域内和具有无碳栅电极的硅碳S / D区域的n-FET结构的实施方案。在非晶化区域内含有碳，确保在再结晶后所有碳都是取代的，以最大限度地增加通道区域上施加的拉伸应力。在碳注入期间，栅极堆叠被封盖，从而基本上消除了碳进入栅极堆叠并降低栅极多晶硅的导电性和/或损坏栅极氧化物的风险。因此，可以更深地形成碳注入区域。完全非晶化然后再结晶的深S / D碳植入物在n-FET沟道区域上提供更大的拉伸应力，以进一步优化电子迁移率。此外，在n型掺杂剂处理期间，栅电极未被封装，因此栅电极中的n型掺杂剂剂量可以至少大于S / D区域中的剂量。

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