专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110012202A1 Selective Floating Body SRAM Cell 有权
公开(公告)号：US20110012202A1
公开(公告)日：2011-01-20
申请号：US12505824
申请日：2009-07-20
申请人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/088 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/1207 , H01L27/1211 , H01L29/7841
摘要： A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.

2. 发明授权

US08349670B2 Selective floating body SRAM cell 有权
标题翻译：选择性浮体SRAM单元
公开(公告)号：US08349670B2
公开(公告)日：2013-01-08
申请号：US13045756
申请日：2011-03-11
申请人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
IPC分类号： H01L21/00
CPC分类号： H01L27/088 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/1207 , H01L27/1211 , H01L29/7841
摘要： A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.
摘要翻译：存储单元具有N≥6个晶体管，其中两个是存取晶体管，至少一对[例如（N-2）/ 2]是上拉晶体管，并且至少另一对[例如（N-2）/ 2 ]是下拉晶体管。上拉和下拉晶体管都耦合在两个存取晶体管之间。每个存取晶体管和上拉晶体管是相同类型的，p型或n型。每个下拉晶体管是另一种类型的p型或n型。存取晶体管是浮体装置。下拉晶体管是非浮体器件。上拉晶体管可以是浮动或非浮动体器件。还详细描述了制造存储器单元的各种具体实施方式和方法。

3. 发明授权

US08378429B2 Selective floating body SRAM cell 有权
标题翻译：选择性浮体SRAM单元
公开(公告)号：US08378429B2
公开(公告)日：2013-02-19
申请号：US13045784
申请日：2011-03-11
申请人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
IPC分类号： H01L21/70
CPC分类号： H01L27/088 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/1207 , H01L27/1211 , H01L29/7841
摘要： A memory cell has N≧16 transistors, in which two are access transistors, at least one pair [say (N-2)/2] are pull-up transistors, and at least another pair [say (N-2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.
摘要翻译：存储单元具有N≥16个晶体管，其中两个是存取晶体管，至少一对[例如（N-2）/ 2]是上拉晶体管，并且至少另一对[例如（N-2）/ 2 ]是下拉晶体管。上拉和下拉晶体管都耦合在两个存取晶体管之间。每个存取晶体管和上拉晶体管是相同类型的，p型或n型。每个下拉晶体管是另一种类型的p型或n型。存取晶体管是浮体装置。下拉晶体管是非浮体器件。上拉晶体管可以是浮动或非浮动体器件。还详细描述了制造存储器单元的各种具体实施方式和方法。

4. 发明授权

US08018007B2 Selective floating body SRAM cell 有权
标题翻译：选择性浮体SRAM单元
公开(公告)号：US08018007B2
公开(公告)日：2011-09-13
申请号：US12505824
申请日：2009-07-20
申请人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
IPC分类号： H01L21/70
CPC分类号： H01L27/088 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/1207 , H01L27/1211 , H01L29/7841
摘要： A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.
摘要翻译：存储单元具有N≥6个晶体管，其中两个是存取晶体管，至少一对[例如（N-2）/ 2]是上拉晶体管，并且至少另一对[例如（N-2）/ 2 ]是下拉晶体管。上拉和下拉晶体管都耦合在两个存取晶体管之间。每个存取晶体管和上拉晶体管是相同类型的，p型或n型。每个下拉晶体管是另一种类型的p型或n型。存取晶体管是浮体装置。下拉晶体管是非浮体器件。上拉晶体管可以是浮动或非浮动体器件。还详细描述了制造存储器单元的各种具体实施方式和方法。

5. 发明申请

US20110204445A1 Selective Floating Body SRAM Cell 有权
标题翻译：选择性浮体SRAM单元
公开(公告)号：US20110204445A1
公开(公告)日：2011-08-25
申请号：US13045784
申请日：2011-03-11
申请人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L27/088
CPC分类号： H01L27/088 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/1207 , H01L27/1211 , H01L29/7841
摘要： A memory cell has N≧16 transistors, in which two are access transistors, at least one pair [say (N-2)/2] are pull-up transistors, and at least another pair [say (N-2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.
摘要翻译：存储单元具有N≥16个晶体管，其中两个是存取晶体管，至少一对[例如（N-2）/ 2]是上拉晶体管，并且至少另一对[例如（N-2）/ 2 ]是下拉晶体管。上拉和下拉晶体管都耦合在两个存取晶体管之间。每个存取晶体管和上拉晶体管是相同类型的，p型或n型。每个下拉晶体管是另一种类型的p型或n型。存取晶体管是浮体装置。下拉式晶体管是非浮体式器件。上拉晶体管可以是浮动或非浮动体器件。还详细描述了制造存储器单元的各种具体实施方式和方法。

6. 发明申请

US20110171790A1 Selective Floating Body SRAM Cell 有权
标题翻译：选择性浮体SRAM单元
公开(公告)号：US20110171790A1
公开(公告)日：2011-07-14
申请号：US13045756
申请日：2011-03-11
申请人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
IPC分类号： H01L21/84
CPC分类号： H01L27/088 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/1207 , H01L27/1211 , H01L29/7841
摘要： A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.
摘要翻译：存储单元具有N≥6个晶体管，其中两个是存取晶体管，至少一对[例如（N-2）/ 2]是上拉晶体管，并且至少另一对[例如（N-2）/ 2 ]是下拉晶体管。上拉和下拉晶体管都耦合在两个存取晶体管之间。每个存取晶体管和上拉晶体管是相同类型的，p型或n型。每个下拉晶体管是另一种类型的p型或n型。存取晶体管是浮体装置。下拉晶体管是非浮体器件。上拉晶体管可以是浮动或非浮动体器件。还详细描述了制造存储器单元的各种具体实施方式和方法。

7. 发明授权

US09513244B2 Ultra-compact, passive, varactor-based wireless sensor using quantum capacitance effect in graphene 有权
标题翻译：超小型，无源，基于变容二极管的无线传感器，在石墨烯中使用量子电容效应
公开(公告)号：US09513244B2
公开(公告)日：2016-12-06
申请号：US14111753
申请日：2012-04-13
申请人： Steven J. Koester
发明人： Steven J. Koester
IPC分类号： H01L21/20 , G01N27/22 , H01L29/10 , H01L29/16 , H01L29/423 , H01L29/93 , H01L31/08 , H01L31/115 , G01R27/26
CPC分类号： G01N27/221 , G01N27/227 , G01R27/2605 , H01L29/1025 , H01L29/1606 , H01L29/42312 , H01L29/93 , H01L31/085 , H01L31/115
摘要： An electrical device includes at least one graphene quantum capacitance varactor. In some examples, the graphene quantum capacitance varactor includes an insulator layer, a graphene layer disposed on the insulator layer, a dielectric layer disposed on the graphene layer, a gate electrode formed on the dielectric layer, and at least one contact electrode disposed on the graphene layer and making electrical contact with the graphene layer. In other examples, the graphene quantum capacitance varactor includes an insulator layer, a gate electrode recessed in the insulator layer, a dielectric layer formed on the gate electrode, a graphene layer formed on the dielectric layer, wherein the graphene layer comprises an exposed surface opposite the dielectric layer, and at least one contact electrode formed on the graphene layer and making electrical contact with the graphene layer.
摘要翻译：电气装置包括至少一个石墨烯量子电容变容二极管。在一些示例中，石墨烯量子电容变容二极管包括绝缘体层，设置在绝缘体层上的石墨烯层，设置在石墨烯层上的电介质层，形成在电介质层上的栅极电极，以及设置在绝缘体层上的至少一个接触电极石墨烯层，并与石墨烯层电接触。在其他实例中，石墨烯量子电容变容二极管包括绝缘体层，凹入绝缘体层中的栅电极，形成在栅电极上的电介质层，形成在电介质层上的石墨烯层，其中石墨烯层包括相对的暴露表面所述电介质层和形成在所述石墨烯层上并与所述石墨烯层电接触的至少一个接触电极。

8. 发明申请

US20140145735A1 ULTRA-COMPACT, PASSIVE, VARACTOR-BASED WIRELESS SENSOR USING QUANTUM CAPACITANCE EFFECT IN GRAPHENE 有权
标题翻译：超声波，无源，基于变压器的无线传感器，在图形中使用量子电容效应
公开(公告)号：US20140145735A1
公开(公告)日：2014-05-29
申请号：US14111753
申请日：2012-04-13
申请人： Steven J. Koester
发明人： Steven J. Koester
IPC分类号： G01N27/22 , G01R27/26
CPC分类号： G01N27/221 , G01N27/227 , G01R27/2605 , H01L29/1025 , H01L29/1606 , H01L29/42312 , H01L29/93 , H01L31/085 , H01L31/115
摘要： An electrical device includes at least one graphene quantum capacitance varactor. In some examples, the graphene quantum capacitance varactor includes an insulator layer, a graphene layer disposed on the insulator layer, a dielectric layer disposed on the graphene layer, a gate electrode formed on the dielectric layer, and at least one contact electrode disposed on the graphene layer and making electrical contact with the graphene layer. In other examples, the graphene quantum capacitance varactor includes an insulator layer, a gate electrode recessed in the insulator layer, a dielectric layer formed on the gate electrode, a graphene layer formed on the dielectric layer, wherein the graphene layer comprises an exposed surface opposite the dielectric layer, and at least one contact electrode formed on the graphene layer and making electrical contact with the graphene layer.
摘要翻译：电气装置包括至少一个石墨烯量子电容变容二极管。在一些示例中，石墨烯量子电容变容二极管包括绝缘体层，设置在绝缘体层上的石墨烯层，设置在石墨烯层上的电介质层，形成在电介质层上的栅电极，以及设置在绝缘体层上的至少一个接触电极石墨烯层，并与石墨烯层电接触。在其他实例中，石墨烯量子电容变容二极管包括绝缘体层，凹入绝缘体层中的栅电极，形成在栅电极上的电介质层，形成在电介质层上的石墨烯层，其中石墨烯层包括相对的暴露表面所述电介质层和形成在所述石墨烯层上并与所述石墨烯层电接触的至少一个接触电极。

9. 发明授权

US08298914B2 3D integrated circuit device fabrication using interface wafer as permanent carrier 有权
标题翻译：使用接口晶片作为永久载体的3D集成电路器件制造
公开(公告)号：US08298914B2
公开(公告)日：2012-10-30
申请号：US12194198
申请日：2008-08-19
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L21/4763
CPC分类号： H01L25/0657 , H01L21/6835 , H01L25/18 , H01L25/50 , H01L2221/68377 , H01L2224/0401 , H01L2224/05001 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05558 , H01L2224/05568 , H01L2224/0557 , H01L2224/056 , H01L2224/131 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/83 , H01L2224/11 , H01L2924/014 , H01L2924/00014
摘要： A method is provided for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer. Also provided is a tangible computer readable medium encoded with a program that comprises instructions for performing such a method.
摘要翻译：提供了一种用于制造3D集成电路结构的方法。提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。第一有源电路层晶片被结合到界面晶片。然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。还提供了一种用包括用于执行这种方法的指令的程序编码的有形计算机可读介质。

10. 发明申请

US20120118383A1 Autonomous Integrated Circuit 审中-公开
标题翻译：自主集成电路
公开(公告)号：US20120118383A1
公开(公告)日：2012-05-17
申请号：US12946216
申请日：2010-11-15
申请人： Stephen W. Bedell , Norma E. Sosa Cortes , Wilfried E. Haensch , Steven J. Koester , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi , Davood Shahrjerdi
发明人： Stephen W. Bedell , Norma E. Sosa Cortes , Wilfried E. Haensch , Steven J. Koester , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi , Davood Shahrjerdi
IPC分类号： H01L31/0264 , H01L31/18
CPC分类号： H01L27/142 , H01L31/02008 , H01L31/0747 , H01L31/075 , H01L31/076 , H01L31/078 , H01L31/1804 , H01L31/202 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： An autonomous integrated circuit (IC) includes a solar cell formed on a bottom substrate of a silicon-on-insulator (SOI) substrate as a handle substrate; an insulating layer of the SOI substrate located on top of the solar cell; and a device layer formed on a top semiconductor layer of the SOI substrate located on top of the insulating layer, wherein a top contact of the device layer is electrically connected to a bottom contact of the solar cell such that the solar cell is enabled to power the device layer.
摘要翻译：自主集成电路（IC）包括形成在作为处理衬底的绝缘体上硅（SOI）衬底的底部衬底上的太阳能电池; 位于太阳能电池顶部的SOI衬底的绝缘层; 以及形成在位于绝缘层顶部的SOI衬底的顶部半导体层上的器件层，其中器件层的顶部接触电连接到太阳能电池的底部接触，使得太阳能电池能够通电设备层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式