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91. 发明授权

US07358573B2 Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same 失效
标题翻译：具有增加的闩锁抗扰度的三阱CMOS器件及其制造方法
公开(公告)号：US07358573B2
公开(公告)日：2008-04-15
申请号：US11683454
申请日：2007-03-08
申请人： Delbert R. Cecchi , Toshiharu Furukawa , Jack Allan Mandelman
发明人： Delbert R. Cecchi , Toshiharu Furukawa , Jack Allan Mandelman
IPC分类号： H01L29/76
CPC分类号： H01L27/0921 , H01L27/0928 , H01L29/1087 , H01L29/7833
摘要： A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.
摘要翻译：具有减小的闩锁磁化率的三阱CMOS结构和制造该结构的方法。该方法包括在P阱下形成具有低电阻的掩埋P型掺杂层和形成CMOS晶体管的N阱，并在P阱中形成的掩埋N型掺杂层中形成间隙，在与P阱的接触下对齐的间隙。埋入的P型掺杂层和掩埋N型掺杂层中的间隙允许在CMOS晶体管的寄生双极晶体管周围的低电阻空穴电流路径。

92. 发明授权

US07268400B2 Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same 有权
标题翻译：具有增加的闩锁抗扰度的三阱CMOS器件及其制造方法
公开(公告)号：US07268400B2
公开(公告)日：2007-09-11
申请号：US11340344
申请日：2006-01-26
申请人： Delbert R. Cecchi , Toshiharu Furukawa , Jack Allan Mandelman
发明人： Delbert R. Cecchi , Toshiharu Furukawa , Jack Allan Mandelman
IPC分类号： H01L29/76
CPC分类号： H01L27/0921 , H01L27/0928 , H01L29/1087 , H01L29/7833
摘要： A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.
摘要翻译：具有减小的闩锁磁化率的三阱CMOS结构和制造该结构的方法。该方法包括在P阱下形成具有低电阻的掩埋P型掺杂层和形成CMOS晶体管的N阱，并在P阱中形成的掩埋N型掺杂层中形成间隙，在与P阱的接触下对齐的间隙。埋入的P型掺杂层和掩埋N型掺杂层中的间隙允许在CMOS晶体管的寄生双极晶体管周围的低电阻空穴电流路径。

93. 发明授权

US07129138B1 Methods of implementing and enhanced silicon-on-insulator (SOI) box structures 失效
标题翻译：实现和增强绝缘体上硅（SOI）盒结构的方法
公开(公告)号：US07129138B1
公开(公告)日：2006-10-31
申请号：US11106004
申请日：2005-04-14
申请人： Toshiharu Furukawa , Carl John Radens , William Robert Tonti , Richard Quimby Williams
发明人： Toshiharu Furukawa , Carl John Radens , William Robert Tonti , Richard Quimby Williams
IPC分类号： H01L21/762
CPC分类号： H01L29/66772 , H01L21/84 , H01L23/5252 , H01L27/1203 , H01L2924/0002 , Y10S438/928 , H01L2924/00
摘要： Enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. An oxygen implant step is performed from a backside into a thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer. The oxygen implant step forms an isolated region near the oxygen implants. A backside implant step selectively dopes the isolated region for forming a backgate for an SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices.
摘要翻译：提供了增强的绝缘体上硅（SOI）掩埋氧化物（BOX）结构和方法来实现增强的SOI BOX结构。将氧注入步骤从背面进行到薄化的硅衬底层。退火步骤从硅衬底层中的氧注入形成厚的掩埋氧化物（BOX）区域。氧注入步骤在氧植入物附近形成隔离区域。背侧注入步骤选择性地掺杂用于形成包括所选择的抗熔丝（AF）器件的SOI器件的SOI器件的隔离区域以及包括PFET和NFET器件的SOI晶体管的隔离区域。

94. 发明授权

US07250351B2 Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistors 失效
标题翻译：增强的绝缘体上硅（SOI）晶体管和制造增强型SOI晶体管的方法
公开(公告)号：US07250351B2
公开(公告)日：2007-07-31
申请号：US11106002
申请日：2005-04-14
申请人： Toshiharu Furukawa , Carl John Radens , William Robert Tonti , Richard Quimby Williams
发明人： Toshiharu Furukawa , Carl John Radens , William Robert Tonti , Richard Quimby Williams
IPC分类号： H01L29/76
CPC分类号： H01L29/78687 , H01L21/26533 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66545 , H01L29/66772 , H01L29/7842 , H01L29/7848 , H01L29/78603
摘要： Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.
摘要翻译：提供了增强的绝缘体上硅晶体管和方法，用于实现增强的绝缘体上硅晶体管。增强型绝缘体上硅（SOI）晶体管包括在SOI源极/漏极扩散下的器件沟道下的薄的掩埋氧化物（BOX）层和厚的自对准埋氧（BOX）区。在源极/漏极区域中使用选择性外延生长来实现适当的应变以同时增强PFET和NFET器件。

95. 发明授权

US08110483B2 Forming an extremely thin semiconductor-on-insulator (ETSOI) layer 有权
标题翻译：形成极薄的绝缘体上半导体（ETSOI）层
公开(公告)号：US08110483B2
公开(公告)日：2012-02-07
申请号：US12603737
申请日：2009-10-22
申请人： Wagdi W. Abadeer , Lilian Kamal, legal representative , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要翻译：公开了用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

96. 发明申请

US20120098087A1 FORMING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER 审中-公开
标题翻译：形成极薄的半导体绝缘体（ETSOI）层
公开(公告)号：US20120098087A1
公开(公告)日：2012-04-26
申请号：US13342423
申请日：2012-01-03
申请人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L27/12 , H01L21/306 , H01L21/3065 , H01L21/265
CPC分类号： H01L29/0649 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要翻译：用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

97. 发明申请

US20110095366A1 FORMING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER 有权
标题翻译：形成极薄的半导体绝缘体（ETSOI）层
公开(公告)号：US20110095366A1
公开(公告)日：2011-04-28
申请号：US12603737
申请日：2009-10-22
申请人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L29/786 , H01L21/762 , H01L29/02
CPC分类号： H01L29/0649 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要翻译：公开了用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

98. 发明申请

US20120208356A1 Device component forming method with a trim step prior to sidewall image transfer (SIT) processing 审中-公开
标题翻译：在侧壁图像转印（SIT）处理之前具有修整步骤的装置部件形成方法
公开(公告)号：US20120208356A1
公开(公告)日：2012-08-16
申请号：US13456282
申请日：2012-04-26
申请人： Toshiharu Furukawa , David V. Horak , Charles W. Koburger, III , Qiqing C. Ouyang
发明人： Toshiharu Furukawa , David V. Horak , Charles W. Koburger, III , Qiqing C. Ouyang
IPC分类号： H01L21/20 , H01L21/302
CPC分类号： H01L21/28132 , H01L21/0337 , H01L21/0338 , H01L29/66795
摘要： Disclosed is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.
摘要翻译：公开了一种用于将部件形状（例如散热片，栅电极等）图案化成基板的成像方法。通过在执行加法或减损侧壁图像转移处理之前进行修整步骤，该方法避免了在硬掩模中形成环形图案，并且因此避免了后SIT工艺修整步骤，需要修剪蒙版对准亚光刻特征以形成具有离散片段的硬掩模图案。在一个实施例中，在进行添加SIT处理之前修剪硬掩模，使得不形成环形图案。在另一个实施例中，用于形成心轴的氧化物层和记忆层在进行减法SIT处理之前被修整。然后在氧化层的回蚀刻期间使用掩模来保护心轴的部分，使得不形成环形图案。

99. 发明申请

US20120018806A1 SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE WITH SELECTIVELY PLACED SUB-INSULATOR LAYER VOID(S) AND METHOD OF FORMING THE SOI STRUCTURE 有权
标题翻译：具有选择性的绝缘子层绝缘体的半导体绝缘体（SOI）结构和形成SOI结构的方法
公开(公告)号：US20120018806A1
公开(公告)日：2012-01-26
申请号：US12842146
申请日：2010-07-23
申请人： Toshiharu Furukawa , Robert R. Robison , Richard Q. Williams
发明人： Toshiharu Furukawa , Robert R. Robison , Richard Q. Williams
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/66477 , H01L21/02104 , H01L21/84 , H01L27/1203 , H01L29/78648 , H01L29/78654
摘要： Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed is an associated method of forming such an SOI structure.
摘要翻译：公开了一种绝缘体半导体（SOI）结构，其具有选择性地放置在衬底中的次绝缘体层空穴，使得半导体层的第一部分与衬底之间的电容耦合将小于第二半导体层和衬底的截面。第一部分可以包含绝缘体层上的第一器件，第二部分可以在绝缘体层上包含第二器件。或者，第一和第二部分可以包括绝缘体层上相同器件的不同区域。例如，在SOI场效应晶体管（FET）中，可以将子绝缘体层空隙选择性地放置在源极，漏极和/或体接触扩散区域下方的衬底中，但不能在沟道区域下方，使得电容耦合这些各种扩散区域和衬底将小于沟道区域和衬底之间的电容耦合。此外，公开了形成这种SOI结构的相关方法。

100. 发明授权

US08039334B2 Shared gate for conventional planar device and horizontal CNT 有权
标题翻译：常规平面器件和水平CNT的共用门
公开(公告)号：US08039334B2
公开(公告)日：2011-10-18
申请号：US12902944
申请日：2010-10-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
IPC分类号： H01L21/8234
CPC分类号： H01L21/823412 , B01J23/74 , B01J37/0238 , B82Y10/00 , H01L21/7624 , H01L21/823437 , H01L27/286 , H01L51/0048 , H01L51/0545 , H01L51/055 , Y10S977/742 , Y10S977/762 , Y10S977/763
摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
摘要翻译：在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管晶体管位于至少一个平面半导体器件的栅极之上。

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