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1. 发明授权

US07268400B2 Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same 有权
标题翻译：具有增加的闩锁抗扰度的三阱CMOS器件及其制造方法
公开(公告)号：US07268400B2
公开(公告)日：2007-09-11
申请号：US11340344
申请日：2006-01-26
申请人： Delbert R. Cecchi , Toshiharu Furukawa , Jack Allan Mandelman
发明人： Delbert R. Cecchi , Toshiharu Furukawa , Jack Allan Mandelman
IPC分类号： H01L29/76
CPC分类号： H01L27/0921 , H01L27/0928 , H01L29/1087 , H01L29/7833
摘要： A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.
摘要翻译：具有减小的闩锁磁化率的三阱CMOS结构和制造该结构的方法。该方法包括在P阱下形成具有低电阻的掩埋P型掺杂层和形成CMOS晶体管的N阱，并在P阱中形成的掩埋N型掺杂层中形成间隙，在与P阱的接触下对齐的间隙。埋入的P型掺杂层和掩埋N型掺杂层中的间隙允许在CMOS晶体管的寄生双极晶体管周围的低电阻空穴电流路径。

2. 发明授权

US07358573B2 Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same 失效
标题翻译：具有增加的闩锁抗扰度的三阱CMOS器件及其制造方法
公开(公告)号：US07358573B2
公开(公告)日：2008-04-15
申请号：US11683454
申请日：2007-03-08
申请人： Delbert R. Cecchi , Toshiharu Furukawa , Jack Allan Mandelman
发明人： Delbert R. Cecchi , Toshiharu Furukawa , Jack Allan Mandelman
IPC分类号： H01L29/76
CPC分类号： H01L27/0921 , H01L27/0928 , H01L29/1087 , H01L29/7833
摘要： A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.
摘要翻译：具有减小的闩锁磁化率的三阱CMOS结构和制造该结构的方法。该方法包括在P阱下形成具有低电阻的掩埋P型掺杂层和形成CMOS晶体管的N阱，并在P阱中形成的掩埋N型掺杂层中形成间隙，在与P阱的接触下对齐的间隙。埋入的P型掺杂层和掩埋N型掺杂层中的间隙允许在CMOS晶体管的寄生双极晶体管周围的低电阻空穴电流路径。

3. 发明授权

US07348793B2 Method and apparatus for detection and prevention of bulk CMOS latchup 失效
标题翻译：用于检测和防止大容量CMOS闭锁的方法和装置
公开(公告)号：US07348793B2
公开(公告)日：2008-03-25
申请号：US11335766
申请日：2006-01-19
申请人： Delbert R. Cecchi
发明人： Delbert R. Cecchi
IPC分类号： G01R31/26
CPC分类号： G01R31/2853
摘要： A method and apparatus are provided for detection and prevention of bulk complementary metal oxide semiconductor (CMOS) latchup. A separate power distribution is provided for coupling a positive voltage supply rail to the N well and a ground voltage supply rail to the P well of the CMOS circuit. At least one sensor monitors current flow in a bias voltage applied to at least one of an N well and a P well of the CMOS circuitry. A latchup event is detected responsive to a predefined increase in the monitored current flow. A switch temporarily interrupts the connection of at least one of the N well and the P well to the respective voltage supply rail when the latchup event is detected.
摘要翻译：提供了用于检测和防止体互补金属氧化物半导体（CMOS）闭锁的方法和装置。提供了一个单独的功率分配，用于将正电压供电导轨连接到N阱，并将接地电压电源线连接到CMOS电路的P阱。至少一个传感器监视施加到CMOS电路的N阱和P阱中的至少一个的偏置电压中的电流。响应于所监视的电流的预定增加来检测闭锁事件。当检测到闭锁事件时，开关暂时中断N阱和P阱中的至少一个与相应的电源供应轨的连接。

4. 发明申请

US20090293024A1 Detecting Circuit Design Limitations and Stresses Via Enhanced Waveform and Schematic Display 审中-公开
标题翻译：通过增强型波形和原理图显示检测电路设计限制和应力
公开(公告)号：US20090293024A1
公开(公告)日：2009-11-26
申请号：US12126157
申请日：2008-05-23
申请人： Richard Scott Brink , Delbert R. Cecchi , Michael Robert Curry , Raymond Alan Richetta , Timothy Joseph Schmerbeck
发明人： Richard Scott Brink , Delbert R. Cecchi , Michael Robert Curry , Raymond Alan Richetta , Timothy Joseph Schmerbeck
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/74
摘要： A method and apparatus are provided for implementing enhanced detection of circuit design limitations and stresses via enhanced waveform and schematic display. A selected simulation is run, for example, a transient, an AC, or a DC simulation. Then a displayed schematic highlights problem areas using a color set selected by a circuit designer.
摘要翻译：提供了一种方法和装置，用于通过增强的波形和示意性显示来实现电路设计限制和应力的增强检测。运行选择的模拟，例如，瞬态，AC或DC模拟。然后，显示的示意图突出显示使用由电路设计者选择的颜色集的问题区域。

5. 发明授权

US06690196B1 Simultaneous bi-directional I/O system 有权
标题翻译：同时双向I / O系统
公开(公告)号：US06690196B1
公开(公告)日：2004-02-10
申请号：US10216617
申请日：2002-08-08
申请人： Delbert R. Cecchi , Daniel N. De Araujo , Daniel M. Dreps , John S. Mitby
发明人： Delbert R. Cecchi , Daniel N. De Araujo , Daniel M. Dreps , John S. Mitby
IPC分类号： H03K190175
CPC分类号： H04L5/1423
摘要： A system for transmitting and receiving data between the near end to the far end of a transmission line. The system has simultaneous bi-directional (SBIDI) drivers and receivers for high performance over well behaved transmission lines. The SBIDI drivers and SBIDI receivers are enabled and disabled by logic inputs. A unidirectional (UNI) receiver is connected in parallel with each SBIDI receivers. Logic insures that the SBIDI and UNI receivers are not enabled at the same time. When desired, the SBIDI receivers are disabled and the UNI receivers enabled and signaling is done unidirectional. The current level in the SBIDI drivers may be modified in response to mode compensation signals to improve signal to noise in the unidirectional mode and to compensate for losses in the simultaneous bi-directional mode. The system may be integrated into all I/O's for maximum design flexibility.
摘要翻译：一种用于在传输线的远端之间发送和接收数据的系统。该系统具有同步双向（SBIDI）驱动器和接收器，用于在性能良好的传输线路上实现高性能。 SBIDI驱动器和SBIDI接收器由逻辑输入启用和禁用。单向（UNI）接收器与每个SBIDI接收器并联连接。逻辑保证SBIDI和UNI接收器不被同时启用。当需要时，SBIDI接收器被禁用，并且UNI接收器被启用，并且信令是单向的。可以响应于模式补偿信号修改SBIDI驱动器中的当前电平，以改善单向模式中的信噪比并补偿同时双向模式中的损耗。该系统可以集成到所有I / O中，以实现最大的设计灵活性。

6. 发明授权

US5727231A Method for personalizing integrated circuit devices 失效
标题翻译：个性化集成电路器件的方法
公开(公告)号：US5727231A
公开(公告)日：1998-03-10
申请号：US651019
申请日：1996-05-21
申请人： Gerald K. Bartley , Delbert R. Cecchi , Jeffrey A. Collett , Linda S. Herman , David O. Lewis , Glenn W. Sellers
发明人： Gerald K. Bartley , Delbert R. Cecchi , Jeffrey A. Collett , Linda S. Herman , David O. Lewis , Glenn W. Sellers
IPC分类号： G06F13/10 , G06F11/00 , G06F13/14 , G06F15/78 , G06F17/50 , G06F13/374
CPC分类号： G06F15/7867 , G06F11/006
摘要： A customizable integrated circuit device is disclosed that is capable of having unique data selected for controlling the functionality or configurability of the integrated circuit. The integrated circuit device has a microcontroller unit, a plurality of function units, coupled to the microcontroller unit, and a novel customization logic unit, also coupled to the microcontroller unit. A plurality of signal selectors, further coupled to the customization logic, either on the integrated circuit or on the mounting module to which the integrated circuit is afixed, are selected to control a signal generated by the customization logic to the microcontroller. The customization logic unit may use data that represents a serial number, performance characteristics, such as operational speed, or qualified external working configurations, such as mainstore or caching configurations, associated with the integrated circuit and as selected by the signal selectors.
摘要翻译：公开了一种可定制的集成电路装置，其能够具有选择用于控制集成电路的功能或可配置性的唯一数据。集成电路器件具有微控制器单元，耦合到微控制器单元的多个功能单元，以及也耦合到微控制器单元的新型定制逻辑单元。多个信号选择器进一步耦合到集成电路或集成电路所固定的安装模块上的定制逻辑，以将由定制逻辑产生的信号控制到微控制器。定制逻辑单元可以使用表示与集成电路相关并由信号选择器选择的序列号，性能特征（诸如操作速度）或合格的外部工作配置（例如主仓或高速缓存配置）的数据。

7. 发明授权

US4902916A Identification of defects in emitter-coupled logic circuits 失效
标题翻译：识别发射极耦合逻辑电路中的缺陷
公开(公告)号：US4902916A
公开(公告)日：1990-02-20
申请号：US270880
申请日：1988-11-14
申请人： Delbert R. Cecchi , Nghia van Phan
发明人： Delbert R. Cecchi , Nghia van Phan
IPC分类号： G01R31/317 , G01R31/30 , H03K19/00 , H03K19/086
CPC分类号： G01R31/30
摘要： An ECL logic circuit uses a single resistor in place of separate current-source and emitter-follower resistors. A single tap connects a point on this resistor to the ground bus, and the signal-output line connects to this resistor by a contact which is separate from the contact connecting the emitter of the ouput transistor to the resistor.

8. 发明授权

US06504417B1 Active trim circuit for CMOS on-chip resistors 失效
标题翻译：用于CMOS片上电阻的主动微调电路
公开(公告)号：US06504417B1
公开(公告)日：2003-01-07
申请号：US09930670
申请日：2001-08-15
申请人： Delbert R. Cecchi , Charles C. Hanson , Curtis W. Preuss
发明人： Delbert R. Cecchi , Charles C. Hanson , Curtis W. Preuss
IPC分类号： H03L500
CPC分类号： H01L27/0802
摘要： A resistance circuit includes an off-chip resistor having a precision resistance; a plurality of on-chip switchable resistors, each of which is capable being switched so as to be coupled in parallel to a nominal resistor; and a resistance comparison unit. The resistance comparison unit compares a plurality of on-chip comparison resistors to the off-chip resistor and couples a number of the on-chip switchable resistors to the nominal resistor so that the combined resistance of the parallel combination of the nominal resistor and the coupled on-chip switchable resistors is within a predetermined range of the precision resistance.
摘要翻译：电阻电路包括具有精度电阻的片外电阻器; 多个片上可切换电阻器，每个电容器能够被切换成与标称电阻器并联耦合; 和电阻比较单元。电阻比较单元将多个片上比较电阻器与片外电阻器进行比较，并将多个片上可切换电阻器耦合到标称电阻器，使得标称电阻器和耦合的并联组合的组合电阻片上可切换电阻在精密电阻的预定范围内。

9. 发明授权

US4866308A CMOS to GPI interface circuit 失效
标题翻译： CMOS到GPI接口电路
公开(公告)号：US4866308A
公开(公告)日：1989-09-12
申请号：US179699
申请日：1988-04-11
申请人： Delbert R. Cecchi , Hyung S. Kim , John S. Mitby , David P. Swart , Balsha R. Stanisic , Philip T. Wu
发明人： Delbert R. Cecchi , Hyung S. Kim , John S. Mitby , David P. Swart , Balsha R. Stanisic , Philip T. Wu
IPC分类号： H03K5/02 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/018521 , H03K19/00361
摘要： A high speed, high performance CMOS to GPI interface circuit is disclosed. The interface circuit contains an input stage, clamping circuitry, an output stage and feedback circuitry. The clamping circuitry clamps the voltage level presented to the output stage at a level below the power supply voltage when the input from the CMOS circuit is at a high logic level. As the voltage level of the signal presented to the CPI circuitry rises, feedback circuitry feeds this signal back to the clamping circuitry, which in turn decreases the voltage level presented to the output stage. This assures the signal presented to the GPI circuit falls within the specified voltage level from 1.51 and 2.2 volts. The feedback circuitry contains a single pole filter that filters out high frequency reflections presented to the feedback circuitry, and a slew rate limiter that slows the rise and fall of the voltage level presented to the output stage thereby reducing noise on the power supply and ground lines. The feedback circuitry uses bilateral (push-pull) gain techniques to control the voltage level presented to the output stage as the input signal from the CMOS circuit swings from low to high logic levels. The interface circuit is made up exclusively from standard threshold FETs. The interface circuit also contains discharge circuitry that discharges the voltage level of the feedback circuitry when the input from the CMOS circuit changes from a high level to a low level, thereby preventing a latch-up condition.

10. 发明授权

US06933743B2 Dual mode analog differential and CMOS logic circuit 有权
标题翻译：双模式模拟差分和CMOS逻辑电路
公开(公告)号：US06933743B2
公开(公告)日：2005-08-23
申请号：US10718219
申请日：2003-11-20
申请人： Delbert R. Cecchi , Michael Launsbach , Curtis Walter Preuss , David W. Siljenberg
发明人： Delbert R. Cecchi , Michael Launsbach , Curtis Walter Preuss , David W. Siljenberg
IPC分类号： G01R31/3167 , G01R31/317 , H03K19/094 , H03K19/00
CPC分类号： H03K19/09432 , G01R31/3167 , G01R31/31701
摘要： A dual mode, analog differential and complementary metal oxide semiconductor (CMOS) logic circuit is provided. The circuit includes a differential input for receiving a differential input signal. A switch pair is coupled to the differential input. A pair of load resistors coupled to the switch pair defines a differential output for providing a differential output signal. A current source is coupled to the switch pair. A control input receives a control signal and control circuitry coupled to the control input disable the current source to select a CMOS testing mode responsive to the control signal being activated.
摘要翻译：提供了双模式，模拟差分和互补金属氧化物半导体（CMOS）逻辑电路。该电路包括用于接收差分输入信号的差分输入。开关对耦合到差分输入。耦合到开关对的一对负载电阻器限定用于提供差分输出信号的差分输出。电流源耦合到开关对。控制输入接收控制信号，并且耦合到控制输入的控制电路禁用电流源以响应于被激活的控制信号来选择CMOS测试模式。

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