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91. 发明申请

US20060029745A1 High throughput ILD fill process for high aspect ratio gap fill 审中-公开
标题翻译：高通量ILD填充过程，用于高纵横比间隙填充
公开(公告)号：US20060029745A1
公开(公告)日：2006-02-09
申请号：US10470618
申请日：2003-01-02
申请人： Gurtej Sandhu
发明人： Gurtej Sandhu
IPC分类号： H05H1/24 , B44C1/22 , C23C16/00
CPC分类号： H01L21/02274 , C23C16/045 , C23C16/401 , C23C16/402 , C23C16/505 , H01J37/321 , H01J2237/3327 , H01L21/02164 , H01L21/31612 , H01L21/31629 , H01L21/76224
摘要： A method for filling gaps in high aspect ratio patterned features on an integrated circuit using plasma CVD processes. A plasma is generated by an inert gas and process gases including silicon and oxygen components. The plasma causes the product gases to react and deposit onto the substrate and concurrently etch the deposited film. During an initial stage, the net deposition rate is kept low to improve filling of the high aspect ratio features, while during one or more later stages the net deposition rate is increased to provide a more conformal film at a higher throughput.
摘要翻译：一种使用等离子体CVD工艺在集成电路上填充高纵横比图案特征的间隙的方法。通过惰性气体和包括硅和氧组分的工艺气体产生等离子体。等离子体使产物气体反应并沉积到基底上并同时蚀刻沉积的膜。在初始阶段期间，净沉积速率保持较低以改善高纵横比特征的填充，而在一个或多个后续阶段期间，净沉积速率增加以提供更高生产量的更保形膜。

92. 发明申请

US20060014386A1 Small grain size, conformal aluminum interconnects and method for their formation 有权
公开(公告)号：US20060014386A1
公开(公告)日：2006-01-19
申请号：US11230773
申请日：2005-09-20
申请人： Wing-Cheong Lai , Gurtej Sandhu
发明人： Wing-Cheong Lai , Gurtej Sandhu
IPC分类号： H01L21/44
CPC分类号： H01L21/76876 , H01L21/28556 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L21/76877
摘要： A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain orientation. Finally, an aluminum film is formed on the second layer of titanium nitride. Optionally, a titanium silicide layer is formed on the semiconductor structure prior to the step of forming the first layer of titanium nitride. Interconnects formed according to the invention have polycrystalline aluminum films with grain sizes of approximately less than 0.25 microns.

93. 发明申请

US20060001019A1 Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same 有权
公开(公告)号：US20060001019A1
公开(公告)日：2006-01-05
申请号：US11216415
申请日：2005-08-30
申请人： Gurtej Sandhu , Pierre Fazan
发明人： Gurtej Sandhu , Pierre Fazan
IPC分类号： H01L29/06 , H01L29/08
CPC分类号： H01L21/7687 , H01L21/76846 , H01L21/76849 , H01L21/76855 , H01L21/76895 , H01L27/10852 , H01L27/10855 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode including a barrier layer interposed between a conductive plug and an oxidation resistant layer. A layer of titanium silicide is fabricated to lie between the conductive plug and the oxidation resistant layer. An insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant.

94. 发明申请

US20050287816A1 Methods of forming patterned photoresist layers over semiconductor substrates 有权
标题翻译：在半导体衬底上形成图案化光致抗蚀剂层的方法
公开(公告)号：US20050287816A1
公开(公告)日：2005-12-29
申请号：US10879367
申请日：2004-06-28
申请人： Guy Blalock , Gurtej Sandhu , Jon Daley
发明人： Guy Blalock , Gurtej Sandhu , Jon Daley
IPC分类号： G03F7/09 , H01L21/027 , H01L21/31 , H01L21/469 , H01L21/4763 , H01L21/768
CPC分类号： G03F7/091 , H01L21/0276
摘要： This invention includes methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a porous antireflective coating is formed over a semiconductor substrate. A photoresist footer-reducing fluid is provided within pores of the porous antireflective coating. A positive photoresist is formed over the porous antireflective coating having the fluid therein. The positive photoresist is patterned and developed to form a patterned photoresist layer, with the fluid within the pores being effective to reduce photoresist footing in the patterned photoresist layer than would otherwise occur in the absence of the fluid within the pores. Other aspects and implementations are contemplated.
摘要翻译：本发明包括在半导体衬底上形成图案化光致抗蚀剂层的方法。在一个实施方案中，在半导体衬底上形成多孔抗反射涂层。在多孔抗反射涂层的孔内提供光致抗蚀剂页脚还原液。在其中具有流体的多孔抗反射涂层上形成正性光致抗蚀剂。正性光致抗蚀剂被图案化和显影以形成图案化的光致抗蚀剂层，孔内的流体有效地减少图案化光致抗蚀剂层中的光致抗蚀剂底脚，而不是在孔内不存在流体的情况下发生。考虑了其他方面和实现。

95. 发明申请

US20050266624A1 Boron incorporated diffusion barrier material 有权
标题翻译：硼掺入扩散阻挡材料
公开(公告)号：US20050266624A1
公开(公告)日：2005-12-01
申请号：US11119370
申请日：2005-04-29
申请人： Vishnu Agarwal , Gurtej Sandhu
发明人： Vishnu Agarwal , Gurtej Sandhu
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/532 , H01L29/49
CPC分类号： H01L21/28088 , H01L21/28061 , H01L21/76841 , H01L23/53257 , H01L29/4941 , H01L29/4966 , H01L2924/0002 , H01L2924/00
摘要： A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a CVD process. The diffusion barrier layer is of particular utility in conjunction with tungsten or tungsten silicide conductive layers formed by CVD.
摘要翻译：公开了一种包括TiN x B B y y的扩散阻挡层，用于保护集成晶体管中的栅极氧化物层。可以通过首先形成TiN层然后将硼掺入到TiN层中来制造扩散阻挡层。扩散阻挡层也可以通过使用包括硼的TDMAT工艺来形成TiN层的方法来制造。扩散阻挡层也可以通过使用CVD工艺形成TiN x B层Y 3层来制造。扩散阻挡层特别适用于通过CVD形成的钨或硅化钨导电层。

96. 发明申请

US20050255698A1 Chemical vapor deposition of titanim 失效
标题翻译：钛的化学气相沉积
公开(公告)号：US20050255698A1
公开(公告)日：2005-11-17
申请号：US11146609
申请日：2005-06-07
申请人： Gurtej Sandhu , Donald Westmoreland
发明人： Gurtej Sandhu , Donald Westmoreland
IPC分类号： C23C16/02 , C23C16/06 , H01L21/285 , H01L21/44 , H01L21/768
CPC分类号： H01L21/76858 , C23C16/0281 , C23C16/045 , C23C16/06 , C23C16/08 , C23C16/56 , H01L21/28518 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76855 , H01L21/76856 , H01L21/76876 , Y10S257/906 , Y10T428/12674 , Y10T428/12743 , Y10T428/31678
摘要： A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed layer by CVD. The titanium layer is used to form contacts to active areas of substrate and for the formation of interlevel vias.
摘要翻译：在化学气相沉积（CVD）的基板上形成钛层。首先，通过CVD将第一前体与还原剂组合在基板上形成种子层。然后，通过CVD通过将第二前体与种子层组合而在基板上形成钛层。钛层用于与衬底的有源区形成接触并形成层间通孔。

97. 发明申请

US20050230735A1 Methods for forming conductive structures and structures regarding same 失效
标题翻译：形成导电结构和结构的方法
公开(公告)号：US20050230735A1
公开(公告)日：2005-10-20
申请号：US11146827
申请日：2005-06-07
申请人： Cem Basceri , Gurtej Sandhu
发明人： Cem Basceri , Gurtej Sandhu
IPC分类号： H01L21/02 , H01L21/768 , H01L27/108 , H01L29/76
CPC分类号： H01L28/75 , H01L21/76888 , H01L28/55 , H01L28/84
摘要： A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g., ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g, ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.
摘要翻译：一种形成金属/金属氧化物结构的方法，其包括在金属层例如铂的晶界处形成金属氧化物区域，例如氧化钌区域。优选地，金属氧化物区域通过氧气通过金属层例如铂的晶界的扩散而形成，以氧化其上的金属层，例如钌层。该结构对于用于诸如动态随机存取存储器（DRAM）器件的电容器结构和存储器件尤为有利。

98. 发明申请

US20050227431A1 Memory device with platinum-rhodium stack as an oxygen barrier 审中-公开
标题翻译：具有铂 - 铑叠层的存储器件作为氧气屏障
公开(公告)号：US20050227431A1
公开(公告)日：2005-10-13
申请号：US11138809
申请日：2005-05-26
申请人： Haining Yang , Gurtej Sandhu
发明人： Haining Yang , Gurtej Sandhu
IPC分类号： C23C16/18 , H01L21/02 , H01L21/285 , H01L21/8242
CPC分类号： H01L28/75 , C23C16/18 , H01L21/28556 , H01L21/28568 , H01L27/1085 , H01L28/55 , H01L28/65 , H01L28/84 , H01L28/90
摘要： The present invention relates to an electrically conductive film stack for semiconductors and methods and apparatus for providing same. A film stack comprising a first layer of a platinum-rhodium alloy deposited by metal organic chemical vapor deposition (MOCVD) in the presence of a reducer, such as hydrogen (H2) gas, and a second layer of the platinum-rhodium alloy deposited in the presence of an oxidizing gas, such as ozone (O3), provides an electrical conductor that is also a relatively good barrier to oxygen. The platinum-rhodium film stack can be used as an electrode or capacitor plate for a capacitor with a high-k dielectric material. The electrode formed with alternating reducing and oxidizing agents produces a rough surface texture, which enhances the memory cell capacitance.
摘要翻译：本发明涉及一种用于半导体的导电膜叠层及其提供方法和装置。一种薄膜叠层，包括在还原剂例如氢（H 2/2））气体存在下通过金属有机化学气相沉积（MOCVD）沉积的铂 - 铑合金的第一层和第二层在氧化气体如臭氧（O 3 3 N）的存在下沉积的铂 - 铑合金提供了也是相对较好的氧阻挡层的电导体。铂 - 铑膜叠层可用作具有高k电介质材料的电容器的电极或电容器板。用交替的还原和氧化剂形成的电极产生粗糙的表面纹理，这增强了存储单元电容。

99. 发明授权

US06952051B1 Interlevel dielectric structure 失效
标题翻译：电介质结构
公开(公告)号：US06952051B1
公开(公告)日：2005-10-04
申请号：US09627649
申请日：2000-07-28
申请人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
发明人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76837
摘要： An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.
摘要翻译：层间电介质结构包括第一和第二电介质层，它们之间位于导电材料的导线之间，其中电介质材料位于导电材料线之间的空间中，电介质材料的下表面延伸低于导电线路的下表面材料相邻，并且电介质材料的上表面比邻近导电材料的上表面延伸得更高，从而减少导电材料线之间的条纹和总电容。具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工。公开了形成层间电介质结构的各种方法。

100. 发明授权

US06940112B2 Integrated capacitors fabricated with conductive metal oxides 失效
标题翻译：用导电金属氧化物制成的集成电容器
公开(公告)号：US06940112B2
公开(公告)日：2005-09-06
申请号：US10234351
申请日：2002-08-30
申请人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
发明人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
IPC分类号： C23C16/40 , H01L21/02 , H01L21/76
CPC分类号： H01L28/60 , C23C16/40 , H01L28/55 , H01L28/90
摘要： A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.
摘要翻译：用于存储器件的电容器形成有用于底部电极的导电氧化物。导电氧化物（RuO x S）在低温下作为非晶膜沉积。结果，膜被共形沉积在三维折叠结构上。此外，随后的研磨步骤容易地在非晶膜上进行，提高了晶片生产量。沉积和抛光后，膜在非氧化环境中结晶。

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