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1. 发明授权

US07705389B2 Thickened sidewall dielectric for memory cell 有权
标题翻译：用于存储单元的增厚的侧壁电介质
公开(公告)号：US07705389B2
公开(公告)日：2010-04-27
申请号：US11847183
申请日：2007-08-29
申请人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
发明人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
摘要翻译：公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上方形成一个控制栅极。在一些实施例中，电荷捕获结构包括纳米点。在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

2. 发明申请

US20120032252A1 THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL 有权
标题翻译：用于记忆体的厚度小的电介质
公开(公告)号：US20120032252A1
公开(公告)日：2012-02-09
申请号：US13276600
申请日：2011-10-19
申请人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
发明人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
摘要翻译：公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上方形成一个控制栅极。在一些实施例中，电荷捕获结构包括纳米点。在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

3. 发明授权

US08058140B2 Thickened sidewall dielectric for memory cell 有权
标题翻译：用于存储单元的增厚的侧壁电介质
公开(公告)号：US08058140B2
公开(公告)日：2011-11-15
申请号：US12757869
申请日：2010-04-09
申请人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
发明人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
IPC分类号： H01L21/76
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
摘要翻译：公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上方形成一个控制栅极。在一些实施例中，电荷捕获结构包括纳米点。在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

4. 发明申请

US20100197131A1 THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL 有权
标题翻译：用于记忆体的厚度小的电介质
公开(公告)号：US20100197131A1
公开(公告)日：2010-08-05
申请号：US12757869
申请日：2010-04-09
申请人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
发明人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
IPC分类号： H01L21/302
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
摘要翻译：公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上方形成一个控制栅极。在一些实施例中，电荷捕获结构包括纳米点。在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

5. 发明授权

US08643082B2 Thickened sidewall dielectric for memory cell 有权
标题翻译：用于存储单元的增厚的侧壁电介质
公开(公告)号：US08643082B2
公开(公告)日：2014-02-04
申请号：US13276600
申请日：2011-10-19
申请人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
发明人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
摘要翻译：公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上形成一个控制栅极。在一些实施例中，电荷捕获结构包括纳米点。在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

6. 发明申请

US20090057744A1 THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL 有权
标题翻译：用于记忆体的厚度小的电介质
公开(公告)号：US20090057744A1
公开(公告)日：2009-03-05
申请号：US11847183
申请日：2007-08-29
申请人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
发明人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
摘要翻译：公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上方形成一个控制栅极。在一些实施例中，电荷捕获结构包括纳米点。在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

7. 发明授权

US06940112B2 Integrated capacitors fabricated with conductive metal oxides 失效
标题翻译：用导电金属氧化物制成的集成电容器
公开(公告)号：US06940112B2
公开(公告)日：2005-09-06
申请号：US10234351
申请日：2002-08-30
申请人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
发明人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
IPC分类号： C23C16/40 , H01L21/02 , H01L21/76
CPC分类号： H01L28/60 , C23C16/40 , H01L28/55 , H01L28/90
摘要： A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.
摘要翻译：用于存储器件的电容器形成有用于底部电极的导电氧化物。导电氧化物（RuO x S）在低温下作为非晶膜沉积。结果，膜被共形沉积在三维折叠结构上。此外，随后的研磨步骤容易地在非晶膜上进行，提高了晶片生产量。沉积和抛光后，膜在非氧化环境中结晶。

8. 发明授权

US06869877B2 Integrated capacitors fabricated with conductive metal oxides 失效
标题翻译：用导电金属氧化物制成的集成电容器
公开(公告)号：US06869877B2
公开(公告)日：2005-03-22
申请号：US10234581
申请日：2002-08-30
申请人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
发明人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
IPC分类号： C23C16/40 , H01L21/02 , H01L21/44
CPC分类号： H01L28/60 , C23C16/40 , H01L28/55 , H01L28/90
摘要： A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.
摘要翻译：用于存储器件的电容器形成有用于底部电极的导电氧化物。导电氧化物（RuOx）在低温下作为非晶膜沉积。结果，膜被共形沉积在三维折叠结构上。此外，随后的研磨步骤容易地在非晶膜上进行，提高了晶片生产量。沉积和抛光后，膜在非氧化环境中结晶。

9. 发明授权

US06492241B1 Integrated capacitors fabricated with conductive metal oxides 有权
标题翻译：用导电金属氧化物制成的集成电容器
公开(公告)号：US06492241B1
公开(公告)日：2002-12-10
申请号：US09546492
申请日：2000-04-10
申请人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
发明人： Howard E. Rhodes , Mark Visokay , Tom Graettinger , Dan Gealy , Gurtej Sandhu , Cem Basceri , Steve Cummings
IPC分类号： H01L2972
CPC分类号： H01L28/60 , C23C16/40 , H01L28/55 , H01L28/90
摘要： A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.
摘要翻译：用于存储器件的电容器形成有用于底部电极的导电氧化物。导电氧化物（RuOx）在低温下作为非晶膜沉积。结果，膜被共形沉积在三维折叠结构上。此外，随后的研磨步骤容易地在非晶膜上进行，提高了晶片生产量。沉积和抛光后，膜在非氧化环境中结晶。

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