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1. 发明授权

US06952051B1 Interlevel dielectric structure 失效
标题翻译：电介质结构
公开(公告)号：US06952051B1
公开(公告)日：2005-10-04
申请号：US09627649
申请日：2000-07-28
申请人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
发明人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76837
摘要： An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.
摘要翻译：层间电介质结构包括第一和第二电介质层，它们之间位于导电材料的导线之间，其中电介质材料位于导电材料线之间的空间中，电介质材料的下表面延伸低于导电线路的下表面材料相邻，并且电介质材料的上表面比邻近导电材料的上表面延伸得更高，从而减少导电材料线之间的条纹和总电容。具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工。公开了形成层间电介质结构的各种方法。

2. 发明授权

US07642204B2 Methods of forming fluorine doped insulating materials 失效
标题翻译：形成氟掺杂绝缘材料的方法
公开(公告)号：US07642204B2
公开(公告)日：2010-01-05
申请号：US10769430
申请日：2004-01-30
申请人： Anand Srinivasan , Gurtej Sandhu , Ravi Iyer
发明人： Anand Srinivasan , Gurtej Sandhu , Ravi Iyer
IPC分类号： H01L21/316
CPC分类号： H01L21/02131 , C23C16/401 , H01L21/02271 , H01L21/31629
摘要： In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants. In yet another aspect, the invention includes a method of forming a phosphorus-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising triethoxy fluorosilane, a phosphorus-containing precursor, and ozone within the reaction chamber; and c) depositing a phosphorus-doped silicon oxide having Si—F bonds onto the substrate from the reactants.
摘要翻译：一方面，本发明包括一种形成绝缘材料的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含Si，F和臭氧的反应物; 以及c）从所述反应物沉积包含氟，硅和氧的绝缘材料到所述衬底上。另一方面，本发明包括形成具有Si-F键的掺硼氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含硼前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的掺硼氧化硅到所述衬底上。另一方面，本发明包括形成具有Si-F键的磷掺杂氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含磷前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的磷掺杂的氧化硅到所述衬底上。

3. 发明授权

US06841463B1 Interlevel dielectric structure and method of forming same 失效
标题翻译：电介质结构及其形成方法
公开(公告)号：US06841463B1
公开(公告)日：2005-01-11
申请号：US09627381
申请日：2000-07-28
申请人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
发明人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76837
摘要： An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.
摘要翻译：层间电介质结构包括第一和第二电介质层，它们之间位于导电材料的导线之间，其中电介质材料位于导电材料线之间的空间中，电介质材料的下表面延伸低于导电线路的下表面材料相邻，并且电介质材料的上表面比邻近导电材料的上表面延伸得更高，从而减少导电材料线之间的条纹和总电容。具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工。公开了形成层间电介质结构的各种方法。

4. 发明授权

US06727190B2 Method of forming fluorine doped boron-phosphorous silicate glass (F-BPSG) insulating materials 失效
标题翻译：氟掺杂硼硅酸盐玻璃（F-BPSG）绝缘材料的形成方法
公开(公告)号：US06727190B2
公开(公告)日：2004-04-27
申请号：US09146839
申请日：1998-09-03
申请人： Anand Srinivasan , Gurtej Sandhu , Ravi Iyer
发明人： Anand Srinivasan , Gurtej Sandhu , Ravi Iyer
IPC分类号： H01L21316
CPC分类号： H01L21/02131 , C23C16/401 , H01L21/02271 , H01L21/31629
摘要： In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants. In yet another aspect, the invention includes a method of forming a phosphorus-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising triethoxy fluorosilane, a phosphorus-containing precursor, and ozone within the reaction chamber; and c) depositing a phosphorus-doped silicon oxide having Si—F bonds onto the substrate from the reactants.
摘要翻译：一方面，本发明包括一种形成绝缘材料的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含Si，F和臭氧的反应物; 以及c）从所述反应物沉积包含氟，硅和氧的绝缘材料到所述衬底上。另一方面，本发明包括形成具有Si-F键的掺硼氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含硼前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的掺硼氧化硅到所述衬底上。另一方面，本发明包括形成具有Si-F键的磷掺杂氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含磷前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的磷掺杂的氧化硅到所述衬底上。

5. 发明授权

US6107686A Interlevel dielectric structure 有权
标题翻译：电介质结构
公开(公告)号：US6107686A
公开(公告)日：2000-08-22
申请号：US249659
申请日：1999-02-12
申请人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
发明人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76837
摘要： An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.
摘要翻译：层间电介质结构包括第一和第二电介质层，它们之间位于导电材料的导线之间，其中电介质材料位于导电材料线之间的空间中，电介质材料的下表面延伸低于导电线路的下表面材料相邻，并且电介质材料的上表面比邻近导电材料的上表面延伸得更高，从而减少导电材料线之间的条纹和总电容。具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工。公开了形成层间电介质结构的各种方法。

6. 发明授权

US6107183A Method of forming an interlevel dielectric 失效
标题翻译：形成层间电介质的方法
公开(公告)号：US6107183A
公开(公告)日：2000-08-22
申请号：US677514
申请日：1996-07-10
申请人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
发明人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76837
摘要： An interlevel dielectric structure includes forming first and second dielectric layers between which are located lines of a conductive material that are also formed with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.
摘要翻译：层间电介质结构包括形成第一和第二电介质层，它们之间位于导电材料的定位线之间，导电材料的导电材料线之间的空间中还形成介电材料，电介质材料的下表面延伸低于下部电介质材料与其相邻的导电材料的线的表面，并且电介质材料的上表面比与其相邻的导电材料的上表面延伸，从而减少导电材料线之间的条纹和总电容。具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工。公开了形成层间电介质结构的各种方法。

7. 发明授权

US5985767A Facet etch for improved step coverage of integrated circuit contacts 有权
标题翻译：方面蚀刻，以改善集成电路触点的台阶覆盖
公开(公告)号：US5985767A
公开(公告)日：1999-11-16
申请号：US228725
申请日：1999-01-12
申请人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L23/485 , H01L23/532 , H01L21/00
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76862 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L21/76844 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.
摘要翻译：公开了一种用于提供与导电材料，特别是金属的接触的改进的台阶覆盖的方法。在接触开口形成之前或之后，在绝缘层上沉积导电层。在导电层沉积和接触形成之后，进行小面蚀刻以使覆盖接触唇的导电层倾斜，同时将材料从导电层沉积到接触的下角，其中覆盖传统上较差。然后可以将第二导电层沉积到接触中以补充由第一导电层提供的覆盖层和小面蚀刻。

8. 发明授权

US5963832A Removal of metal cusp for improved contact fill 有权
公开(公告)号：US5963832A
公开(公告)日：1999-10-05
申请号：US184489
申请日：1998-11-02
申请人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/768 , H01L23/485 , H01L21/285
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76844 , H01L21/76855 , H01L21/76862 , H01L21/76864 , H01L21/76877 , H01L23/485 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.

9. 发明授权

US5929526A Removal of metal cusp for improved contact fill 失效
公开(公告)号：US5929526A
公开(公告)日：1999-07-27
申请号：US870105
申请日：1997-06-05
申请人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/768 , H01L23/485 , H01L23/48
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76844 , H01L21/76855 , H01L21/76862 , H01L21/76864 , H01L21/76877 , H01L23/485 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.

10. 发明授权

US5861344A Facet etch for improved step coverage of integrated circuit contacts 失效
公开(公告)号：US5861344A
公开(公告)日：1999-01-19
申请号：US958655
申请日：1997-10-27
申请人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L23/485 , H01L23/532 , H01L21/00
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76862 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L21/76844 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.

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