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1. 发明授权

US06952051B1 Interlevel dielectric structure 失效
标题翻译：电介质结构
公开(公告)号：US06952051B1
公开(公告)日：2005-10-04
申请号：US09627649
申请日：2000-07-28
申请人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
发明人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76837
摘要： An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.
摘要翻译：层间电介质结构包括第一和第二电介质层，它们之间位于导电材料的导线之间，其中电介质材料位于导电材料线之间的空间中，电介质材料的下表面延伸低于导电线路的下表面材料相邻，并且电介质材料的上表面比邻近导电材料的上表面延伸得更高，从而减少导电材料线之间的条纹和总电容。具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工。公开了形成层间电介质结构的各种方法。

2. 发明授权

US6107686A Interlevel dielectric structure 有权
标题翻译：电介质结构
公开(公告)号：US6107686A
公开(公告)日：2000-08-22
申请号：US249659
申请日：1999-02-12
申请人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
发明人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76837
摘要： An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.
摘要翻译：层间电介质结构包括第一和第二电介质层，它们之间位于导电材料的导线之间，其中电介质材料位于导电材料线之间的空间中，电介质材料的下表面延伸低于导电线路的下表面材料相邻，并且电介质材料的上表面比邻近导电材料的上表面延伸得更高，从而减少导电材料线之间的条纹和总电容。具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工。公开了形成层间电介质结构的各种方法。

3. 发明授权

US6107183A Method of forming an interlevel dielectric 失效
标题翻译：形成层间电介质的方法
公开(公告)号：US6107183A
公开(公告)日：2000-08-22
申请号：US677514
申请日：1996-07-10
申请人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
发明人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76837
摘要： An interlevel dielectric structure includes forming first and second dielectric layers between which are located lines of a conductive material that are also formed with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.
摘要翻译：层间电介质结构包括形成第一和第二电介质层，它们之间位于导电材料的定位线之间，导电材料的导电材料线之间的空间中还形成介电材料，电介质材料的下表面延伸低于下部电介质材料与其相邻的导电材料的线的表面，并且电介质材料的上表面比与其相邻的导电材料的上表面延伸，从而减少导电材料线之间的条纹和总电容。具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工。公开了形成层间电介质结构的各种方法。

4. 发明授权

US07642204B2 Methods of forming fluorine doped insulating materials 失效
标题翻译：形成氟掺杂绝缘材料的方法
公开(公告)号：US07642204B2
公开(公告)日：2010-01-05
申请号：US10769430
申请日：2004-01-30
申请人： Anand Srinivasan , Gurtej Sandhu , Ravi Iyer
发明人： Anand Srinivasan , Gurtej Sandhu , Ravi Iyer
IPC分类号： H01L21/316
CPC分类号： H01L21/02131 , C23C16/401 , H01L21/02271 , H01L21/31629
摘要： In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants. In yet another aspect, the invention includes a method of forming a phosphorus-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising triethoxy fluorosilane, a phosphorus-containing precursor, and ozone within the reaction chamber; and c) depositing a phosphorus-doped silicon oxide having Si—F bonds onto the substrate from the reactants.
摘要翻译：一方面，本发明包括一种形成绝缘材料的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含Si，F和臭氧的反应物; 以及c）从所述反应物沉积包含氟，硅和氧的绝缘材料到所述衬底上。另一方面，本发明包括形成具有Si-F键的掺硼氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含硼前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的掺硼氧化硅到所述衬底上。另一方面，本发明包括形成具有Si-F键的磷掺杂氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含磷前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的磷掺杂的氧化硅到所述衬底上。

5. 发明授权

US06841463B1 Interlevel dielectric structure and method of forming same 失效
标题翻译：电介质结构及其形成方法
公开(公告)号：US06841463B1
公开(公告)日：2005-01-11
申请号：US09627381
申请日：2000-07-28
申请人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
发明人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76837
摘要： An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.
摘要翻译：层间电介质结构包括第一和第二电介质层，它们之间位于导电材料的导线之间，其中电介质材料位于导电材料线之间的空间中，电介质材料的下表面延伸低于导电线路的下表面材料相邻，并且电介质材料的上表面比邻近导电材料的上表面延伸得更高，从而减少导电材料线之间的条纹和总电容。具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工。公开了形成层间电介质结构的各种方法。

6. 发明授权

US06727190B2 Method of forming fluorine doped boron-phosphorous silicate glass (F-BPSG) insulating materials 失效
标题翻译：氟掺杂硼硅酸盐玻璃（F-BPSG）绝缘材料的形成方法
公开(公告)号：US06727190B2
公开(公告)日：2004-04-27
申请号：US09146839
申请日：1998-09-03
申请人： Anand Srinivasan , Gurtej Sandhu , Ravi Iyer
发明人： Anand Srinivasan , Gurtej Sandhu , Ravi Iyer
IPC分类号： H01L21316
CPC分类号： H01L21/02131 , C23C16/401 , H01L21/02271 , H01L21/31629
摘要： In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants. In yet another aspect, the invention includes a method of forming a phosphorus-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising triethoxy fluorosilane, a phosphorus-containing precursor, and ozone within the reaction chamber; and c) depositing a phosphorus-doped silicon oxide having Si—F bonds onto the substrate from the reactants.
摘要翻译：一方面，本发明包括一种形成绝缘材料的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含Si，F和臭氧的反应物; 以及c）从所述反应物沉积包含氟，硅和氧的绝缘材料到所述衬底上。另一方面，本发明包括形成具有Si-F键的掺硼氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含硼前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的掺硼氧化硅到所述衬底上。另一方面，本发明包括形成具有Si-F键的磷掺杂氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含磷前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的磷掺杂的氧化硅到所述衬底上。

7. 发明授权

US06888212B2 Method for trench isolation by selective deposition of low temperature oxide films 失效
标题翻译：通过选择性沉积低温氧化膜进行沟槽隔离的方法
公开(公告)号：US06888212B2
公开(公告)日：2005-05-03
申请号：US10254756
申请日：2002-09-24
申请人： Ravi Iyer , Gurtej Sandhu , Pai Pan
发明人： Ravi Iyer , Gurtej Sandhu , Pai Pan
IPC分类号： H01L21/762 , H01L21/208
CPC分类号： H01L21/76224
摘要： A method of forming isolation regions in a silicon substrate comprising the steps of forming a trench in the silicon substrate, filling the trench with a silanol polymer material then heating the silanol polymer material so that silicon dioxide is formed in the trench and thereby forms the isolation region. In the preferred embodiment, the silicon substrate is covered by a masking stack which is then etched to expose the underlying silicon substrate. The silicon substrate is then etched to form the trench and the silanol polymer material is deposited in the trench and fills the trench from the bottom up thereby avoiding divots and other defects. The silanol polymer grows faster on the silicon substrate than it does on the nitride. After the silanol polymer is reacted to form the silicon dioxide, CMP polishing is then used to remove the remaining masking stack and silicon dioxide above the surface of the silicon substrate.
摘要翻译：一种在硅衬底中形成隔离区域的方法，包括以下步骤：在硅衬底中形成沟槽，用硅烷醇聚合物材料填充沟槽，然后加热硅烷醇聚合物材料，使得在沟槽中形成二氧化硅，从而形成隔离地区。在优选实施例中，硅衬底由掩模叠层覆盖，该掩模叠层然后被蚀刻以暴露下面的硅衬底。然后蚀刻硅衬底以形成沟槽，并且硅烷醇聚合物材料沉积在沟槽中并从底部向上填充沟槽，从而避免纹理和其它缺陷。在硅衬底上，硅烷醇聚合物比在氮化物上生长得更快。在硅烷醇聚合物反应形成二氧化硅之后，然后使用CMP研磨去除硅衬底表面上剩余的掩模叠层和二氧化硅。

8. 发明申请

US20050121794A1 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US20050121794A1
公开(公告)日：2005-06-09
申请号：US11026822
申请日：2004-12-29
申请人： Werner Juengling , Kirk Prall , Ravi Iyer , Gurtej Sandhu , Guy Blalock
发明人： Werner Juengling , Kirk Prall , Ravi Iyer , Gurtej Sandhu , Guy Blalock
IPC分类号： H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L29/40
CPC分类号： H01L23/5222 , H01L21/02115 , H01L21/02118 , H01L21/02203 , H01L21/02274 , H01L21/02282 , H01L21/02337 , H01L21/02362 , H01L21/31695 , H01L21/7682 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.
摘要翻译：本发明包括在导电元件之间形成绝缘材料的方法。在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

9. 发明授权

US06455394B1 Method for trench isolation by selective deposition of low temperature oxide films 失效
标题翻译：通过选择性沉积低温氧化膜进行沟槽隔离的方法
公开(公告)号：US06455394B1
公开(公告)日：2002-09-24
申请号：US09041984
申请日：1998-03-13
申请人： Ravi Iyer , Gurtej Sandhu , Pai Pan
发明人： Ravi Iyer , Gurtej Sandhu , Pai Pan
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method of forming isolation regions in a silicon substrate comprising the steps of forming a trench in the silicon substrate, filling the trench with a silanol polymer material then heating the silanol polymer material so that silicon dioxide is formed in the trench and thereby forms the isolation region. In the preferred embodiment, the silicon substrate is covered by a masking stack which is then etched to expose the underlying silicon substrate. The silicon substrate is then etched to form the trench and the silanol polymer material is deposited in the trench and fills the trench from the bottom up thereby avoiding divots and other defects. The silanol polymer grows faster on the silicon substrate than it does on the nitride. After the silanol polymer is reacted to form the silicon dioxide, CMP polishing is then used to remove the remaining masking stack and silicon dioxide above the surface of the silicon substrate.
摘要翻译：一种在硅衬底中形成隔离区的方法，包括以下步骤：在硅衬底中形成沟槽，用硅烷醇聚合物材料填充沟槽，然后加热硅烷醇聚合物材料，使得在沟槽中形成二氧化硅，从而形成隔离地区。在优选实施例中，硅衬底由掩模叠层覆盖，该掩模叠层然后被蚀刻以暴露下面的硅衬底。然后蚀刻硅衬底以形成沟槽，并且硅烷醇聚合物材料沉积在沟槽中并从底部向上填充沟槽，从而避免纹理和其它缺陷。在硅衬底上，硅烷醇聚合物比在氮化物上生长得更快。在硅烷醇聚合物反应形成二氧化硅之后，然后使用CMP研磨去除硅衬底表面上剩余的掩模叠层和二氧化硅。

10. 发明授权

US09076888B2 Silicided recessed silicon 有权
公开(公告)号：US09076888B2
公开(公告)日：2015-07-07
申请号：US11614802
申请日：2006-12-21
申请人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/8238 , H01L21/28 , H01L21/8234 , H01L27/108 , H01L29/49 , H01L29/66
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.

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