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91. 发明授权

US06716742B2 Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics 有权
标题翻译：低k互连结构由多层旋涂多孔电介质组成
公开(公告)号：US06716742B2
公开(公告)日：2004-04-06
申请号：US10292205
申请日：2002-11-12
申请人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
发明人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76811 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.
摘要翻译：提供了其中不存在微沟槽的低k电介质金属导体互连结构以及形成这种结构的方法。具体地说，上述结构是通过提供一种互连结构来实现的，所述互连结构至少包括多层电介质材料，所述多层电介质材料依次应用于单个旋涂工具中，然后在单个步骤中固化，并且多个图案化的金属导体在多层纺丝 - 电介质。使用具有位于具有第一原子组成的多孔低k电介质的线路和通孔电介质层之间的第二原子组成的掩埋蚀刻停止层来获得对导体电阻的控制。本发明的互连结构还包括有助于形成双镶嵌型互连结构的硬掩模。选择第一和第二组合物以获得至少10至1或更高的蚀刻选择性，并且选自具有特定原子组成和其它可发现量的多孔低k有机或无机材料的特定组。

92. 发明授权

US06661098B2 High density area array solder microjoining interconnect structure and fabrication method 有权
标题翻译：高密度区阵列焊料微接合互连结构及制造方法
公开(公告)号：US06661098B2
公开(公告)日：2003-12-09
申请号：US10052620
申请日：2002-01-18
申请人： John Harold Magerlein , Kevin Shawn Petrarca , Sampath Purushothaman , Carlos Juan Sambucetti , Richard Paul Volant , George Frederick Walker
发明人： John Harold Magerlein , Kevin Shawn Petrarca , Sampath Purushothaman , Carlos Juan Sambucetti , Richard Paul Volant , George Frederick Walker
IPC分类号： H01L2348
CPC分类号： H01L24/10 , H01L21/67144 , H01L23/49811 , H01L24/13 , H01L2224/05001 , H01L2224/05023 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/0102 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01046 , H01L2924/01058 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/30105 , H05K1/0306 , H05K1/112 , H05K3/34 , H05K3/3436 , H05K3/388 , H05K2201/0317 , H05K2201/09472 , H05K2201/09509 , H01L2924/00
摘要： A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.
摘要翻译：教导了通过布置在互连载体上的一组微接点互连一组器件芯片的系统。载体具有致密阵列的具有粘附层，阻挡层和贵金属层的微接点插座; 制造器件晶片的阵列包括粘附层，阻挡层和易熔焊料层的微接合焊盘阵列，焊盘位于相对于屏障插座的匹配位置; 所述器件芯片通过微接点阵列连接到所述载体，导致能够实现非常高的输入/输出密度和芯片间布线密度的互连。

93. 发明授权

US06577011B1 Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same 有权
标题翻译：具有低介电常数绝缘体的芯片互连布线结构及其制造方法
公开(公告)号：US06577011B1
公开(公告)日：2003-06-10
申请号：US09715559
申请日：2000-11-17
申请人： Leena P. Buchwalter , Alessandro Cesare Callegari , Stephan Alan Cohen , Teresita Ordonez Graham , John P. Hummel , Christopher V. Jahnes , Sampath Purushothaman , Katherine Lynn Saenger , Jane Margaret Shaw
发明人： Leena P. Buchwalter , Alessandro Cesare Callegari , Stephan Alan Cohen , Teresita Ordonez Graham , John P. Hummel , Christopher V. Jahnes , Sampath Purushothaman , Katherine Lynn Saenger , Jane Margaret Shaw
IPC分类号： H01L2348
CPC分类号： H01L21/7682 , H01L23/5222 , H01L23/53223 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present invention includes a multilevel air-gap-containing interconnect wiring structure including: a collection of interspersed line levels and via levels, the via levels and line levels containing conductive via and line features embedded in a dielectric having an air-gap and solid dielectric. The air-gap and solid dielectric includes (i) one or more solid dielectrics only in the shadows of the conductive features in overlying levels and (ii) a gaseous dielectric elsewhere in the structure. The collection of line levels and via levels are topped by a laminated thin, taut insulating cover layer having openings to selected conductive features in the topmost underlying line or via layer, and the openings are filled with conductive material connecting to terminal pad contacts on the insulating cover layer.
摘要翻译：本发明包括一个多级含气隙的互连配线结构，其包括：散布的线路层级和通孔层的集合，通孔层和线路层包含嵌入在具有空隙和固体电介质的电介质中的导电通孔和线特征。气隙和固体电介质包括（i）仅在覆盖层中的导电特征的阴影中的一个或多个固体电介质，以及（ii）结构中其它地方的气体介电。线路层和通孔层的集合由层叠的薄的，紧密的绝缘覆盖层覆盖，其具有在最上面的下面的线或通孔层中选择的导电特征的开口，并且开口填充有连接到绝缘体上的端子焊盘触点的导电材料覆盖层。

94. 发明授权

US06555762B2 Electronic package having substrate with electrically conductive through holes filled with polymer and conductive composition 有权
标题翻译：电子封装，其具有填充有聚合物和导电组合物的导电通孔的基板
公开(公告)号：US06555762B2
公开(公告)日：2003-04-29
申请号：US09345428
申请日：1999-07-01
申请人： Bernd K. Appelt , Jeffrey D. Gelorme , Sung Kwon Kang , Voya R. Markovich , Kostas Papathomas , Sampath Purushothaman
发明人： Bernd K. Appelt , Jeffrey D. Gelorme , Sung Kwon Kang , Voya R. Markovich , Kostas Papathomas , Sampath Purushothaman
IPC分类号： H05K111
CPC分类号： H01L23/49827 , H01B1/02 , H01B1/22 , H01L23/49866 , H01L2924/0002 , H05K1/095 , H05K3/4069 , Y10T428/12181 , Y10T428/2991 , Y10T428/2993 , Y10T428/2998 , H01L2924/00
摘要： The present invention provides a unique, high density, electronic package having a conductive composition for filling vias or through holes to make reliable vertical or Z-connects from a dielectric layer to adjacent electrical circuits. The through holes may be plated or non-plated prior to filling. A description for making high density electronic packaging using this feature is also disclosed.
摘要翻译：本发明提供了一种独特的，高密度的电子封装，其具有用于填充通孔或通孔的导电组合物，以使得从电介质层到相邻电路的可靠的垂直或Z-连接。通孔可以在填充之前进行镀覆或非电镀。还公开了使用该特征制造高密度电子封装的描述。

95. 发明授权

US06344660B1 Thin-film field-effect transistor with organic semiconductor requiring low operating voltages 有权
标题翻译：具有需要低工作电压的有机半导体的薄膜场效应晶体管
公开(公告)号：US06344660B1
公开(公告)日：2002-02-05
申请号：US09323804
申请日：1999-06-02
申请人： Christos Dimitrios Dimitrakopoulos , Peter Richard Duncombe , Bruce K. Furman , Robert B. Laibowitz , Deborah Ann Neumayer , Sampath Purushothaman
发明人： Christos Dimitrios Dimitrakopoulos , Peter Richard Duncombe , Bruce K. Furman , Robert B. Laibowitz , Deborah Ann Neumayer , Sampath Purushothaman
IPC分类号： H01L3524
CPC分类号： H01L51/0525 , H01L21/31691 , H01L51/0052 , H01L51/0545
摘要： A thin film transistor (TFT) device structure based on an organic semiconductor material, that exhibits a high field effect mobility, high current modulation and a low sub-threshold slope at lower operating voltages than the current state of the art organic TFT devices. The structure comprises a suitable substrate disposed with he following sequence of features: a set of conducting gate electrodes covered with a high dielectric constant insulator, a layer of the organic semiconductor, sets of electrically conducting source and drain electrodes corresponding to each of the gate lines, and an optional passivation layer that can overcoat and protect the device structure. Use of high dielectric constant gate insulators exploits the unexpected gate voltage dependence of the organic semiconductor to achieve high field effect mobility levels at very low operating voltages. Judicious combinations of the choice of this insulator material and the means to integrate it into the TFT structure are taught that would enable easy fabrication on glass or plastic substrates and the use of such devices in flat panel display applications.
摘要翻译：一种基于有机半导体材料的薄膜晶体管（TFT）器件结构，其在比现有技术的有机TFT器件的当前状态更低的工作电压下表现出高场效应迁移率，高电流调制和低子阈值斜率。该结构包括合适的衬底，其具有以下特征序列：一组覆盖有高介电常数绝缘体的导电栅极电极，有机半导体层，对应于每条栅极线的导电源极和漏极电极组，以及可以覆盖和保护器件结构的可选钝化层。使用高介电常数栅极绝缘体利用有机半导体的意想不到的栅极电压依赖性，以在非常低的工作电压下实现高场效应迁移率水平。教导了将这种绝缘体材料的选择和将其集成到TFT结构中的手段的合理组合，这将使得能够容易地在玻璃或塑料基板上制造以及在平板显示器应用中使用这种装置。

96. 发明授权

US06184121B2 Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same 失效
标题翻译：具有低介电常数绝缘体的芯片互连布线结构及其制造方法
公开(公告)号：US06184121B2
公开(公告)日：2001-02-06
申请号：US09112919
申请日：1998-07-09
申请人： Leena P. Buchwalter , Alessandro Cesare Callegari , Stephan Alan Cohen , Teresita Ordonez Graham , John P. Hummel , Christopher V. Jahnes , Sampath Purushothaman , Katherine Lynn Saenger , Jane Margaret Shaw
发明人： Leena P. Buchwalter , Alessandro Cesare Callegari , Stephan Alan Cohen , Teresita Ordonez Graham , John P. Hummel , Christopher V. Jahnes , Sampath Purushothaman , Katherine Lynn Saenger , Jane Margaret Shaw
IPC分类号： H01L214763
CPC分类号： H01L23/53228 , H01L21/7682 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method to achieve a very low effective dielectric constant in high performance back end of the line chip interconnect wiring and the resulting multilayer structure are disclosed. The process involves fabricating the multilayer interconnect wiring structure by methods and materials currently known in the state of the art of semiconductor processing; removing the intralevel dielectric between the adjacent metal features by a suitable etching process; applying a thin passivation coating over the exposed etched structure; annealing the etched structure to remove plasma damage; laminating an insulating cover layer to the top surface of the passivated metal features; optionally depositing an insulating environmental barrier layer on top of the cover layer; etching vias in the environmental barrier layer, cover layer and the thin passivation layer for terminal pad contacts; and completing the device by fabricating terminal input/output pads. The method obviates issues such as processability and thermal stability associated with low dielectric constant materials by avoiding their use. Since air, which has the lowest dielectric constant, is used as the intralevel dielectric the structure created by this method would possess a very low capacitance and hence fast propagation speeds. Such structure is ideally suitable for high density interconnects required in high performance microelectronic device chips.
摘要翻译：公开了一种在线芯片互连布线和所得多层结构的高性能后端中实现非常低的有效介电常数的方法。该方法涉及通过目前在半导体处理领域中已知的方法和材料制造多层互连布线结构; 通过合适的蚀刻工艺去除相邻金属特征之间的层间电介质; 在暴露的蚀刻结构上施加薄的钝化涂层; 退火蚀刻结构以去除等离子体损伤; 将绝缘覆盖层层压到钝化金属特征的顶表面; 可选地在覆盖层的顶部上沉积绝缘环境阻挡层; 在环境阻挡层，覆盖层和用于端子焊盘触点的薄钝化层中蚀刻通孔; 并通过制造端子输入/输出焊盘来完成该器件。该方法通过避免其使用而消除了与低介电常数材料相关的加工性和热稳定性等问题。由于具有最低介电常数的空气被用作体内电介质，所以通过该方法产生的结构将具有非常低的电容并因此具有快速的传播速度。这种结构理想地适用于高性能微电子器件芯片所需的高密度互连。

97. 发明授权

US06120885A Structure, materials, and methods for socketable ball grid 失效
标题翻译：可插座球栅的结构，材料和方法
公开(公告)号：US06120885A
公开(公告)日：2000-09-19
申请号：US106779
申请日：1998-06-30
申请人： Anson J. Call , Stephen Anthony DeLaurentis , Shaji Farooq , Sung Kwon Kang , Sampath Purushothaman , Kathleen Ann Stalter
发明人： Anson J. Call , Stephen Anthony DeLaurentis , Shaji Farooq , Sung Kwon Kang , Sampath Purushothaman , Kathleen Ann Stalter
IPC分类号： H01L23/498 , H05K3/32 , H05K3/34 , H05K3/40 , B32B7/00 , B32B15/16 , H01L23/48 , H01L29/12
CPC分类号： H05K3/3436 , H01L23/49816 , H05K3/4015 , H01L2924/0002 , H05K2201/10234 , H05K2201/10333 , H05K2201/10962 , H05K3/321 , H05K3/3447 , Y02P70/613 , Y10S428/901 , Y10T428/12528 , Y10T428/24917 , Y10T428/256
摘要： A socketable ball grid array structure is disclosed which comprises mechanically rigid (compared to solder alloys) balls coated with noble contact metals joined to the chip carrier terminals by means of a novel electrically conducting adhesive. Because of the nature of the filler that includes conducting particles with a fusible coating and the appropriate selection of the polymer resin used in the adhesive, the balls are attached to the module in a compliant and resilient manner while leaving the majority of the bottom surface of the balls pristine. The array of balls can therefore be plugged into mating sockets in a printed circuit board forming a demountable contact. This facilitates easy removal of the socketable BGA from a board for repair or upgrade purposes as well as allows ease of plugging and unplugging of these BGA's into test and burn-in boards.
摘要翻译：公开了一种可插座的球栅阵列结构，其包括通过新颖的导电粘合剂机械地刚性（与焊料合金相比）涂覆有接合到芯片载体端子的贵金属接触金属的球。由于包括具有可熔涂层的导电颗粒和粘合剂中使用的聚合物树脂的适当选择的填料的性质，球以顺应性和弹性方式附着到模块上，同时留下了大部分的底表面球原始。因此，球阵可以插入形成可拆卸接触的印刷电路板中的配合插座中。这样便于从板上轻松取出可插拔的BGA，以进行修理或升级，同时也可以方便地将这些BGA插入测试和老化板。

98. 发明授权

US6104466A Precision alignment of plates 有权
标题翻译：板的精确对准
公开(公告)号：US6104466A
公开(公告)日：2000-08-15
申请号：US226475
申请日：1999-01-07
申请人： Stephen L. Buchwalter , David A. Lewis , Shui-Chih Alan Lien , Sampath Purushothaman , John J. Ritsko
发明人： Stephen L. Buchwalter , David A. Lewis , Shui-Chih Alan Lien , Sampath Purushothaman , John J. Ritsko
IPC分类号： G02F1/1333 , G02F1/13 , G02F1/0337
CPC分类号： G02F1/1333 , G02F2001/133354
摘要： A system for aligning two plates, in accordance with the present invention, includes a first plate having a lithographically patterned structure formed on a first surface. A second plate also has a lithographically patterned structure formed on a second surface, the first and second surfaces being disposed to face each other. The patterned structures of the plates have corresponding and opposing edges to provide an interference fit between the patterned structures of the first and second plates wherein self-alignment between the first and second plates is realized by engaging the corresponding and opposing edges in the interference fit. A method for aligning two plates includes the steps of providing the system described above, coarsely aligning the plates in a first state which includes an interference between the patterned structures, adjusting at least one of plates to provide a second state having a clearance fit between the patterned structures and moving the plates together and returning to the first state to align the plates relative to each other.
摘要翻译：根据本发明的用于对准两个板的系统包括形成在第一表面上的具有光刻图案化结构的第一板。第二板还具有形成在第二表面上的光刻图案结构，第一和第二表面被设置为彼此面对。板的图案化结构具有对应的和相对的边缘，以在第一和第二板的图案化结构之间提供过盈配合，其中第一和第二板之间的自对准是通过在干涉配合中接合相应和相对的边缘来实现的。一种用于对准两个板的方法包括以下步骤：提供上述系统，在第一状态下将板粗略对准，该第一状态包括图案化结构之间的干涉，调节板中的至少一个以提供第二状态，图案化结构并将板移动到一起并返回到第一状态以使板相对于彼此对准。

99. 发明授权

US6059952A Method of fabricating coated powder materials and their use for high conductivity paste applications 失效
标题翻译：制造涂层粉末材料的方法及其在高导电性浆料应用中的应用
公开(公告)号：US6059952A
公开(公告)日：2000-05-09
申请号：US111155
申请日：1998-07-07
申请人： Sung Kwon Kang , Sampath Purushothaman , Rajinder Singh Rai
发明人： Sung Kwon Kang , Sampath Purushothaman , Rajinder Singh Rai
IPC分类号： C25D17/16 , H01L21/60 , H05K3/32 , C25D5/00 , C23C28/02 , C25D5/34 , C25D5/50 , C25D7/00
CPC分类号： H01L24/83 , C25D17/16 , H01L24/29 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29324 , H01L2224/29339 , H01L2224/29344 , H01L2224/29347 , H01L2224/29355 , H01L2224/29357 , H01L2224/29364 , H01L2224/29369 , H01L2224/29409 , H01L2224/29411 , H01L2224/29413 , H01L2224/29416 , H01L2224/29418 , H01L2224/29499 , H01L2224/83101 , H01L2224/8319 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/0132 , H01L2924/01322 , H01L2924/0133 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/07811 , H01L2924/15787 , H01L2924/351 , H05K3/321
摘要： Methods for forming pastes of powder particles coated with an electrically conductive coating are described. The powder particles, with or without an optional first conductive coating layer applied to their surface, are placed in contact with a cathode surface and immersed in an electroplating solution. An anode covered with a nonconducting but ion-permeable membrane is immersed in the solution in close proximity to the cathode. Agitation to move and gently tumble the powder over the cathode surface is provided. The powder particles are plated with a metal or metal alloy coating by biasing the anode with a positive voltage relative to the cathode. The coated powder is removed, rinsed and dried. The powder is added to a polymer material to form a paste which is heated to fuse the powder coating surfaces to form a network of interconnected particles and is further heated to cure the polymer. When the paste is disposed between adjacent electrically conductive surfaces, the coated particles fuse to the electrically conductive surfaces to form electrical interconnections.
摘要翻译：描述了形成涂有导电涂层的粉末颗粒糊的方法。将具有或不具有施加到其表面的任选的第一导电涂层的粉末颗粒放置成与阴极表面接触并浸入电镀溶液中。用不导电但是离子可渗透的膜覆盖的阳极被浸在靠近阴极的溶液中。提供了在阴极表面上移动并轻轻地滚动粉末的搅动。粉末颗粒通过以相对于阴极的正电压偏置阳极而用金属或金属合金涂层镀覆。去除涂覆的粉末，漂洗并干燥。将粉末加入到聚合物材料中以形成糊状物，其被加热以熔化粉末涂层表面以形成互连颗粒的网络，并进一步加热以固化聚合物。当糊料设置在相邻的导电表面之间时，涂覆的颗粒融合到导电表面以形成电互连。

100. 发明授权

US6020946A Dry processing for liquid-crystal displays using low energy ion bombardment 失效
标题翻译：使用低能离子轰击的液晶显示器的干式处理
公开(公告)号：US6020946A
公开(公告)日：2000-02-01
申请号：US28018
申请日：1998-02-23
申请人： Alessandro Cesare Callegari , Praveen Chaudhari , James Patrick Doyle , James Andrew Lacey , Shui-Chin Alan Lien , Sampath Purushothaman , Mahesh Govind Samant , James L. Speidell , Joachim Stohr
发明人： Alessandro Cesare Callegari , Praveen Chaudhari , James Patrick Doyle , James Andrew Lacey , Shui-Chin Alan Lien , Sampath Purushothaman , Mahesh Govind Samant , James L. Speidell , Joachim Stohr
IPC分类号： G02F1/1337 , C07C1/00
CPC分类号： G02F1/13378 , G02F1/133734 , G02F2001/133765
摘要： The present invention is a method for forming a liquid-crystal cell of a liquid-crystal display. Initially, a dry processed alignment film is deposited onto a first transparent substrate using a dry processing technique, such as plasma enhanced chemical vapor deposition (PECVD). The dry processed alignment film is then irradiated with a beam of atoms to arrange the atomic structure of the alignment film in at least one desired direction in order to orient the liquid-crystal molecules. Another dry processed alignment film is deposited on a second substrate using a dry processing technique and, likewise, irradiated with a beam of atoms. The first transparent substrate and the second substrate are then sandwiched together with their respective alignment films spaced adjacent to each other. The space between the films is then filled with a liquid-crystal material.
摘要翻译：本发明是一种形成液晶显示器的液晶元件的方法。首先，使用诸如等离子体增强化学气相沉积（PECVD）的干法处理技术将干燥处理的取向膜沉积到第一透明基板上。然后用原子束照射干燥处理的取向膜，以将取向膜的原子结构设置在至少一个所需方向上，以便使液晶分子取向。使用干法处理技术将另一干燥处理的取向膜沉积在第二基板上，并且同样用原子束照射。然后将第一透明基板和第二基板夹在一起，并将它们各自的定向膜彼此间隔开。然后用液晶材料填充膜之间的空间。

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