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1. 发明授权

US06577011B1 Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same 有权
标题翻译：具有低介电常数绝缘体的芯片互连布线结构及其制造方法
公开(公告)号：US06577011B1
公开(公告)日：2003-06-10
申请号：US09715559
申请日：2000-11-17
申请人： Leena P. Buchwalter , Alessandro Cesare Callegari , Stephan Alan Cohen , Teresita Ordonez Graham , John P. Hummel , Christopher V. Jahnes , Sampath Purushothaman , Katherine Lynn Saenger , Jane Margaret Shaw
发明人： Leena P. Buchwalter , Alessandro Cesare Callegari , Stephan Alan Cohen , Teresita Ordonez Graham , John P. Hummel , Christopher V. Jahnes , Sampath Purushothaman , Katherine Lynn Saenger , Jane Margaret Shaw
IPC分类号： H01L2348
CPC分类号： H01L21/7682 , H01L23/5222 , H01L23/53223 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present invention includes a multilevel air-gap-containing interconnect wiring structure including: a collection of interspersed line levels and via levels, the via levels and line levels containing conductive via and line features embedded in a dielectric having an air-gap and solid dielectric. The air-gap and solid dielectric includes (i) one or more solid dielectrics only in the shadows of the conductive features in overlying levels and (ii) a gaseous dielectric elsewhere in the structure. The collection of line levels and via levels are topped by a laminated thin, taut insulating cover layer having openings to selected conductive features in the topmost underlying line or via layer, and the openings are filled with conductive material connecting to terminal pad contacts on the insulating cover layer.
摘要翻译：本发明包括一个多级含气隙的互连配线结构，其包括：散布的线路层级和通孔层的集合，通孔层和线路层包含嵌入在具有空隙和固体电介质的电介质中的导电通孔和线特征。气隙和固体电介质包括（i）仅在覆盖层中的导电特征的阴影中的一个或多个固体电介质，以及（ii）结构中其它地方的气体介电。线路层和通孔层的集合由层叠的薄的，紧密的绝缘覆盖层覆盖，其具有在最上面的下面的线或通孔层中选择的导电特征的开口，并且开口填充有连接到绝缘体上的端子焊盘触点的导电材料覆盖层。

2. 发明授权

US06184121B2 Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same 失效
标题翻译：具有低介电常数绝缘体的芯片互连布线结构及其制造方法
公开(公告)号：US06184121B2
公开(公告)日：2001-02-06
申请号：US09112919
申请日：1998-07-09
申请人： Leena P. Buchwalter , Alessandro Cesare Callegari , Stephan Alan Cohen , Teresita Ordonez Graham , John P. Hummel , Christopher V. Jahnes , Sampath Purushothaman , Katherine Lynn Saenger , Jane Margaret Shaw
发明人： Leena P. Buchwalter , Alessandro Cesare Callegari , Stephan Alan Cohen , Teresita Ordonez Graham , John P. Hummel , Christopher V. Jahnes , Sampath Purushothaman , Katherine Lynn Saenger , Jane Margaret Shaw
IPC分类号： H01L214763
CPC分类号： H01L23/53228 , H01L21/7682 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method to achieve a very low effective dielectric constant in high performance back end of the line chip interconnect wiring and the resulting multilayer structure are disclosed. The process involves fabricating the multilayer interconnect wiring structure by methods and materials currently known in the state of the art of semiconductor processing; removing the intralevel dielectric between the adjacent metal features by a suitable etching process; applying a thin passivation coating over the exposed etched structure; annealing the etched structure to remove plasma damage; laminating an insulating cover layer to the top surface of the passivated metal features; optionally depositing an insulating environmental barrier layer on top of the cover layer; etching vias in the environmental barrier layer, cover layer and the thin passivation layer for terminal pad contacts; and completing the device by fabricating terminal input/output pads. The method obviates issues such as processability and thermal stability associated with low dielectric constant materials by avoiding their use. Since air, which has the lowest dielectric constant, is used as the intralevel dielectric the structure created by this method would possess a very low capacitance and hence fast propagation speeds. Such structure is ideally suitable for high density interconnects required in high performance microelectronic device chips.
摘要翻译：公开了一种在线芯片互连布线和所得多层结构的高性能后端中实现非常低的有效介电常数的方法。该方法涉及通过目前在半导体处理领域中已知的方法和材料制造多层互连布线结构; 通过合适的蚀刻工艺去除相邻金属特征之间的层间电介质; 在暴露的蚀刻结构上施加薄的钝化涂层; 退火蚀刻结构以去除等离子体损伤; 将绝缘覆盖层层压到钝化金属特征的顶表面; 可选地在覆盖层的顶部上沉积绝缘环境阻挡层; 在环境阻挡层，覆盖层和用于端子焊盘触点的薄钝化层中蚀刻通孔; 并通过制造端子输入/输出焊盘来完成该器件。该方法通过避免其使用而消除了与低介电常数材料相关的加工性和热稳定性等问题。由于具有最低介电常数的空气被用作体内电介质，所以通过该方法产生的结构将具有非常低的电容并因此具有快速的传播速度。这种结构理想地适用于高性能微电子器件芯片所需的高密度互连。

3. 发明授权

US06815329B2 Multilayer interconnect structure containing air gaps and method for making 有权
标题翻译：包含气隙的多层互连结构和制造方法
公开(公告)号：US06815329B2
公开(公告)日：2004-11-09
申请号：US10117797
申请日：2002-04-02
申请人： Katherina E. Babich , Roy Arthur Carruthers , Timothy Joseph Dalton , Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Ebony Lynn Mays , Laurent Perraud , Sampath Purushothaman , Katherine Lynn Saenger
发明人： Katherina E. Babich , Roy Arthur Carruthers , Timothy Joseph Dalton , Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Ebony Lynn Mays , Laurent Perraud , Sampath Purushothaman , Katherine Lynn Saenger
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/7681 , H01L21/7682 , H01L21/76834 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.
摘要翻译：描述了一种新颖的含气隙的互连布线结构，其在通孔级中结合有固体低k电介质，并且在布线层中结合了复合固体和气隙电介质。还提供了形成这种互连结构的方法。该方法很容易扩展到包含多个布线级别的互连结构，并且与双镶嵌后端（BEOL）处理兼容。

4. 发明授权

US06759321B2 Stabilization of fluorine-containing low-k dielectrics in a metal/insulator wiring structure by ultraviolet irradiation 失效
标题翻译：通过紫外线照射使金属/绝缘体布线结构中的含氟低k电介质稳定化
公开(公告)号：US06759321B2
公开(公告)日：2004-07-06
申请号：US10205526
申请日：2002-07-25
申请人： Katherina Babich , Alessandro Callegari , Stephen Alan Cohen , Alfred Grill , Christopher Vincent Jahnes , Vishnubhai Vitthalbhai Patel , Sampath Purushothaman , Katherine Lynn Saenger
发明人： Katherina Babich , Alessandro Callegari , Stephen Alan Cohen , Alfred Grill , Christopher Vincent Jahnes , Vishnubhai Vitthalbhai Patel , Sampath Purushothaman , Katherine Lynn Saenger
IPC分类号： H01L214763
CPC分类号： H01L21/76825 , H01L21/0212 , H01L21/02274 , H01L21/02348 , H01L21/31058 , H01L21/3127 , H01L21/31629 , H01L21/76814 , H01L21/76828 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for providing regions of substantially lower fluorine content in a fluorine containing dielectric is described incorporating exposing a region to ultraviolet radiation and annealing at an elevated temperature to remove partially disrupted fluorine from the region. The invention overcomes the problem of fluorine from a fluorine containing dielectric reacting with other materials while maintaining a bulk dielectric material of sufficiently high or original fluorine content to maintain an effective low dielectric constant in semiconductor chip wiring interconnect structures.
摘要翻译：描述了在含氟电介质中提供基本上较低氟含量的区域的方法，其包括将区域暴露于紫外线辐射并在升高的温度下退火以从该区域去除部分被破坏的氟。本发明克服了与含氟介质与其他材料反应的氟的问题，同时保持足够高或原始氟含量的体电介质材料，以保持半导体芯片布线互连结构中有效的低介电常数。

5. 发明授权

US06737725B2 Multilevel interconnect structure containing air gaps and method for making 有权
标题翻译：包含气隙的多层互连结构和制造方法
公开(公告)号：US06737725B2
公开(公告)日：2004-05-18
申请号：US10144574
申请日：2002-05-13
申请人： Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Satyanarayana Venkata Nitta , Kevin S. Petrarca , Sampath Purushothaman , Katherine Lynn Saenger , Stanley Joseph Whitehair
发明人： Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Satyanarayana Venkata Nitta , Kevin S. Petrarca , Sampath Purushothaman , Katherine Lynn Saenger , Stanley Joseph Whitehair
IPC分类号： H01L2900
CPC分类号： H01L21/7682 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L21/76885
摘要： A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics. The inventive method includes the steps of: (a) forming a first planar via plus line level pair embedded in a dielectric matrix formed from one or more solid dielectrics and comprising a via level dielectric and a line level dielectric on a substrate, wherein, at least one of said solid dielectrics is at least partially sacrificial; (b) etching back sacrificial portions of said at least partially sacrificial dielectrics are removed to leave cavities extending into and through said via level, while leaving, at least some of the original via level dielectric as a permanent dielectric under said lines; (c) partially filling or overfilling said cavities with a place-holder material which may or may not be sacrificial; (d) planarizing the structure by removing overfill of said place-holder material; (e) repeating, as necessary, steps (a)-(d); (f) forming a dielectric bridge layer over the planar structure; and (g) forming air gaps by at least partially extracting said place-holder material.
摘要翻译：一种在衬底上形成多层互连结构的方法，其包括互连的导电布线和通过固体或气体电介质的组合间隔开的通孔。本发明的方法包括以下步骤：（a）形成嵌入在由一个或多个固体电介质形成的电介质矩阵中并且包括通孔层电介质和衬底上的线路电介质的介电矩阵中的第一平面通孔加线电平对，其中，在至少一个所述固体电介质至少部分地是牺牲的; （b）蚀刻所述至少部分牺牲电介质的牺牲部分被去除以留下延伸进入并穿过所述通孔级的空腔，同时留下至少一些原始通孔级电介质作为所述线下的永久电介质; （c）用可能牺牲或可能不是牺牲的位置保持材料部分填充或过度填充所述空腔; （d）通过去除所述位置保持器材料的过量填充来平坦化结构; （e）必要时重复步骤（a） - （d）; （f）在所述平面结构上形成电介质桥接层; 和（g）通过至少部分地提取所述放置支架材料形成气隙。

6. 发明授权

US07098476B2 Multilayer interconnect structure containing air gaps and method for making 有权
公开(公告)号：US07098476B2
公开(公告)日：2006-08-29
申请号：US10949837
申请日：2004-09-24
申请人： Katherina E. Babich , Roy Arthur Carruthers , Timothy Joseph Dalton , Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Ebony Lynn Mays , Laurent Perraud , Sampath Purushothaman , Katherine Lynn Saenger
发明人： Katherina E. Babich , Roy Arthur Carruthers , Timothy Joseph Dalton , Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Ebony Lynn Mays , Laurent Perraud , Sampath Purushothaman , Katherine Lynn Saenger
IPC分类号： H01L31/20 , H01L29/04
CPC分类号： H01L21/76831 , H01L21/7681 , H01L21/7682 , H01L21/76834 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

7. 发明授权

US06448655B1 Stabilization of fluorine-containing low-k dielectrics in a metal/insulator wiring structure by ultraviolet irradiation 失效
标题翻译：通过紫外线照射使金属/绝缘体布线结构中的含氟低k电介质稳定化
公开(公告)号：US06448655B1
公开(公告)日：2002-09-10
申请号：US09067439
申请日：1998-04-28
申请人： Katherina Babich , Alessandro Callegari , Stephen Alan Cohen , Alfred Grill , Christopher Vincent Jahnes , Vishnubhai Vitthalbhai Patel , Sampath Purushothaman , Katherine Lynn Saenger
发明人： Katherina Babich , Alessandro Callegari , Stephen Alan Cohen , Alfred Grill , Christopher Vincent Jahnes , Vishnubhai Vitthalbhai Patel , Sampath Purushothaman , Katherine Lynn Saenger
IPC分类号： H01L2348
CPC分类号： H01L21/76825 , H01L21/0212 , H01L21/02274 , H01L21/02348 , H01L21/31058 , H01L21/3127 , H01L21/31629 , H01L21/76814 , H01L21/76828 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for providing regions of substantially lower fluorine content in a fluorine containing dielectric is described incorporating exposing a region to ultraviolet radiation and annealing at an elevated temperature to remove partially disrupted fluorine from the region. The invention overcomes the problem of fluorine from a fluorine containing dielectric reacting with other materials while maintaining a bulk dielectric material of sufficiently high or original fluorine content to maintain an effective low dielectric constant in semiconductor chip wiring interconnect structures.
摘要翻译：描述了在含氟电介质中提供基本上较低氟含量的区域的方法，其包括将区域暴露于紫外线辐射并在升高的温度下退火以从该区域去除部分被破坏的氟。本发明克服了与含氟介质与其他材料反应的氟的问题，同时保持足够高或原始氟含量的体电介质材料，以保持半导体芯片布线互连结构中有效的低介电常数。

8. 发明授权

US06413852B1 Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material 有权
标题翻译：形成包含气隙的多层互连结构的方法，包括利用牺牲和占位材料
公开(公告)号：US06413852B1
公开(公告)日：2002-07-02
申请号：US09652754
申请日：2000-08-31
申请人： Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Satyanarayana Venkata Nitta , Kevin S. Petrarca , Sampath Purushothaman , Katherine Lynn Saenger , Stanley Joseph Whitehair
发明人： Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Satyanarayana Venkata Nitta , Kevin S. Petrarca , Sampath Purushothaman , Katherine Lynn Saenger , Stanley Joseph Whitehair
IPC分类号： H01L218234
CPC分类号： H01L21/7682 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L21/76885
摘要： A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics. The inventive method includes the steps of: (a) forming a first planar via plus line level pair embedded in a dielectric matrix formed from one or more solid dielectrics and comprising a via level dielectric and a line level dielectric on a substrate, wherein, at least one of said solid dielectrics is at least partially sacrificial; (b) etching back sacrificial portions of said at least partially sacrificial dielectrics are removed to leave cavities extending into and through said via level, while leaving, at least some of the original via level dielectric as a permanent dielectric under said lines; (c) partially filling or overfilling said cavities with a place-holder material which may or may not be sacrificial; (d) planarizing the structure by removing overfill of said place-holder material; (e) repeating, as necessary, steps (a)-(d); (f) forming a dielectric bridge layer over the planar structure; and (g) forming air gaps by at least partially extracting said place-holder material.
摘要翻译：一种在衬底上形成多层互连结构的方法，其包括互连的导电布线和通过固体或气体电介质的组合间隔开的通孔。本发明的方法包括以下步骤：（a）形成嵌入在由一个或多个固体电介质形成的电介质矩阵中并且包括通孔层电介质和衬底上的线路电介质的介电矩阵中的第一平面通孔加线电平对，其中，在至少一个所述固体电介质至少部分地是牺牲的; （b）蚀刻所述至少部分牺牲电介质的牺牲部分被去除以留下延伸进入并穿过所述通孔级的空腔，同时留下至少一些原始通孔级电介质作为所述线下的永久电介质; （c）用可能牺牲或可能不是牺牲的位置保持材料部分填充或过度填充所述空腔; （d）通过去除所述位置保持器材料的过量填充来平坦化结构; （e）必要时重复步骤（a） - （d）; （f）在所述平面结构上形成电介质桥接层; 和（g）通过至少部分地提取所述放置支架材料形成气隙。

9. 发明授权

US08592280B2 Fin field effect transistor devices with self-aligned source and drain regions 有权
标题翻译： Fin场效应晶体管器件具有自对准的源极和漏极区域
公开(公告)号：US08592280B2
公开(公告)日：2013-11-26
申请号：US12544939
申请日：2009-08-20
申请人： Josephine B. Chang , Michael A. Guillorn , Wilfried Haensch , Katherine Lynn Saenger
发明人： Josephine B. Chang , Michael A. Guillorn , Wilfried Haensch , Katherine Lynn Saenger
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/0886 , H01L29/66545 , H01L29/66553 , H01L29/66795 , H01L29/785 , H01L29/7854 , Y10S977/938
摘要： Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a field effect transistor device comprises the following steps. A substrate is provided having a silicon layer thereon. A fin lithography hardmask is patterned on the silicon layer. A dummy gate structure is placed over a central portion of the fin lithography hardmask. A filler layer is deposited around the dummy gate structure. The dummy gate structure is removed to reveal a trench in the filler layer, centered over the central portion of the fin lithography hardmask, that distinguishes a fin region of the device from source and drain regions of the device. The fin lithography hardmask in the fin region is used to etch a plurality of fins in the silicon layer. The trench is filled with a gate material to form a gate stack over the fins. The filler layer is removed to reveal the source and drain regions of the device, wherein the source and drain regions are intact and self-aligned with the gate stack.
摘要翻译：提供了改进的鳍状场效应晶体管（FinFET）器件及其制造方法。一方面，一种用于制造场效应晶体管器件的方法包括以下步骤。提供其上具有硅层的衬底。翅片光刻硬掩模在硅层上图案化。虚拟栅极结构放置在散热片光刻硬掩模的中心部分上。填充层沉积在伪栅极结构周围。去除伪栅极结构以在填充层中露出位于散热片光刻硬掩模的中心部分上方的沟槽，其将器件的鳍片区域与器件的源极和漏极区域区分开。翅片区域中的翅片光刻硬掩模用于蚀刻硅层中的多个翅片。沟槽填充有栅极材料，以在鳍片上形成栅极叠层。去除填充层以露出器件的源极和漏极区域，其中源极和漏极区域是完整的并且与栅极堆叠自对准。

10. 发明授权

US07217969B2 Flip FERAM cell and method to form same 失效
标题翻译：翻转FERAM细胞和方法形成相同
公开(公告)号：US07217969B2
公开(公告)日：2007-05-15
申请号：US10384002
申请日：2003-03-07
申请人： James William Adkisson , Charles Thomas Black , Alfred Grill , Randy William Mann , Deborah Ann Neumayer , Wilbur David Pricer , Katherine Lynn Saenger , Thomas McCarroll Shaw
发明人： James William Adkisson , Charles Thomas Black , Alfred Grill , Randy William Mann , Deborah Ann Neumayer , Wilbur David Pricer , Katherine Lynn Saenger , Thomas McCarroll Shaw
IPC分类号： H01L29/76
CPC分类号： H01L28/55 , H01L27/0629 , H01L27/11502 , H01L27/11507 , Y10S438/977
摘要： A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.
摘要翻译：提供了一种形成集成的铁电/ CMOS结构的方法，其有效地分离不兼容的高温沉积和退火工艺。本发明的方法包括分别形成CMOS结构和铁电输送晶片。然后使这些分离的结构与每个结构接触，并且通过使用低温退火步骤将输送晶片的铁电体膜结合到CMOS结构的上导电电极层。然后去除输送晶片的一部分，提供集成的FE / CMOS结构，其中铁电电容器形成在CMOS结构的顶部。电容器通过CMOS结构的所有布线级与CMOS结构的晶体管接触。

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