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1. 发明授权

US06577011B1 Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same 有权
标题翻译：具有低介电常数绝缘体的芯片互连布线结构及其制造方法
公开(公告)号：US06577011B1
公开(公告)日：2003-06-10
申请号：US09715559
申请日：2000-11-17
申请人： Leena P. Buchwalter , Alessandro Cesare Callegari , Stephan Alan Cohen , Teresita Ordonez Graham , John P. Hummel , Christopher V. Jahnes , Sampath Purushothaman , Katherine Lynn Saenger , Jane Margaret Shaw
发明人： Leena P. Buchwalter , Alessandro Cesare Callegari , Stephan Alan Cohen , Teresita Ordonez Graham , John P. Hummel , Christopher V. Jahnes , Sampath Purushothaman , Katherine Lynn Saenger , Jane Margaret Shaw
IPC分类号： H01L2348
CPC分类号： H01L21/7682 , H01L23/5222 , H01L23/53223 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present invention includes a multilevel air-gap-containing interconnect wiring structure including: a collection of interspersed line levels and via levels, the via levels and line levels containing conductive via and line features embedded in a dielectric having an air-gap and solid dielectric. The air-gap and solid dielectric includes (i) one or more solid dielectrics only in the shadows of the conductive features in overlying levels and (ii) a gaseous dielectric elsewhere in the structure. The collection of line levels and via levels are topped by a laminated thin, taut insulating cover layer having openings to selected conductive features in the topmost underlying line or via layer, and the openings are filled with conductive material connecting to terminal pad contacts on the insulating cover layer.
摘要翻译：本发明包括一个多级含气隙的互连配线结构，其包括：散布的线路层级和通孔层的集合，通孔层和线路层包含嵌入在具有空隙和固体电介质的电介质中的导电通孔和线特征。气隙和固体电介质包括（i）仅在覆盖层中的导电特征的阴影中的一个或多个固体电介质，以及（ii）结构中其它地方的气体介电。线路层和通孔层的集合由层叠的薄的，紧密的绝缘覆盖层覆盖，其具有在最上面的下面的线或通孔层中选择的导电特征的开口，并且开口填充有连接到绝缘体上的端子焊盘触点的导电材料覆盖层。

2. 发明授权

US06184121B2 Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same 失效
标题翻译：具有低介电常数绝缘体的芯片互连布线结构及其制造方法
公开(公告)号：US06184121B2
公开(公告)日：2001-02-06
申请号：US09112919
申请日：1998-07-09
申请人： Leena P. Buchwalter , Alessandro Cesare Callegari , Stephan Alan Cohen , Teresita Ordonez Graham , John P. Hummel , Christopher V. Jahnes , Sampath Purushothaman , Katherine Lynn Saenger , Jane Margaret Shaw
发明人： Leena P. Buchwalter , Alessandro Cesare Callegari , Stephan Alan Cohen , Teresita Ordonez Graham , John P. Hummel , Christopher V. Jahnes , Sampath Purushothaman , Katherine Lynn Saenger , Jane Margaret Shaw
IPC分类号： H01L214763
CPC分类号： H01L23/53228 , H01L21/7682 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method to achieve a very low effective dielectric constant in high performance back end of the line chip interconnect wiring and the resulting multilayer structure are disclosed. The process involves fabricating the multilayer interconnect wiring structure by methods and materials currently known in the state of the art of semiconductor processing; removing the intralevel dielectric between the adjacent metal features by a suitable etching process; applying a thin passivation coating over the exposed etched structure; annealing the etched structure to remove plasma damage; laminating an insulating cover layer to the top surface of the passivated metal features; optionally depositing an insulating environmental barrier layer on top of the cover layer; etching vias in the environmental barrier layer, cover layer and the thin passivation layer for terminal pad contacts; and completing the device by fabricating terminal input/output pads. The method obviates issues such as processability and thermal stability associated with low dielectric constant materials by avoiding their use. Since air, which has the lowest dielectric constant, is used as the intralevel dielectric the structure created by this method would possess a very low capacitance and hence fast propagation speeds. Such structure is ideally suitable for high density interconnects required in high performance microelectronic device chips.
摘要翻译：公开了一种在线芯片互连布线和所得多层结构的高性能后端中实现非常低的有效介电常数的方法。该方法涉及通过目前在半导体处理领域中已知的方法和材料制造多层互连布线结构; 通过合适的蚀刻工艺去除相邻金属特征之间的层间电介质; 在暴露的蚀刻结构上施加薄的钝化涂层; 退火蚀刻结构以去除等离子体损伤; 将绝缘覆盖层层压到钝化金属特征的顶表面; 可选地在覆盖层的顶部上沉积绝缘环境阻挡层; 在环境阻挡层，覆盖层和用于端子焊盘触点的薄钝化层中蚀刻通孔; 并通过制造端子输入/输出焊盘来完成该器件。该方法通过避免其使用而消除了与低介电常数材料相关的加工性和热稳定性等问题。由于具有最低介电常数的空气被用作体内电介质，所以通过该方法产生的结构将具有非常低的电容并因此具有快速的传播速度。这种结构理想地适用于高性能微电子器件芯片所需的高密度互连。

3. 发明授权

US06428894B1 Tunable and removable plasma deposited antireflective coatings 失效
标题翻译：可调谐和可移除等离子体沉积的抗反射涂层
公开(公告)号：US06428894B1
公开(公告)日：2002-08-06
申请号：US08868772
申请日：1997-06-04
申请人： Katherina E. Babich , Alessandro Cesare Callegari , Julien Fontaine , Alfred Grill , Christopher V. Jahnes , Vishnubhai Vitthalbhai Patel
发明人： Katherina E. Babich , Alessandro Cesare Callegari , Julien Fontaine , Alfred Grill , Christopher V. Jahnes , Vishnubhai Vitthalbhai Patel
IPC分类号： B32B900
CPC分类号： H01L21/02274 , C23C16/26 , C23C16/30 , G03F7/091 , H01L21/02115 , H01L21/02271 , H01L21/0276 , H01L21/31144 , H01L21/312 , H01L21/3127 , Y10T428/24942 , Y10T428/24975 , Y10T428/265 , Y10T428/30
摘要： Disclosed is vapor deposited BARC and method of preparing tunable and removable antireflective coatings based on amorphous carbon films. These films can be hydrogenated, fluorinated, nitrogenated carbon films. Such films have an index of refraction and an extinction coefficient tunable from about 1.4 to about 2.1 and from about 0.1 to about 0.6, respectively, at UV and DUV wavelengths, in particular 365, 248 and 193 nm. Moreover, the films produced by the present invention can be deposited over device topography with high conformality, and they are etchable by oxygen and/or a fluoride ion etch process. Because of their unique properties, these films can be used to form a tunable and removable antireflective coating at UV and DUV wavelengths to produce near zero reflectance at the resist/BARC coating interface. This BARC greatly improves performance of semiconductor chips.
摘要翻译：公开了蒸汽沉积的BARC和基于无定形碳膜制备可调谐和可去除的抗反射涂层的方法。这些膜可以是氢化，氟化，氮化的碳膜。这些膜的折射率和消光系数分别在UV和DUV波长，特别是365,248和193nm处可调，分别为约1.4至约2.1和约0.1至约0.6。此外，由本发明生产的膜可以以高共形性沉积在器件形貌上，并且它们可通过氧和/或氟离子蚀刻工艺进行蚀刻。由于其独特的性质，这些膜可用于在UV和DUV波长处形成可调谐和可去除的抗反射涂层，以在抗蚀剂/ BARC涂层界面处产生接近零的反射率。该BARC大大提高了半导体芯片的性能。

4. 发明授权

US06720249B1 Protective hardmask for producing interconnect structures 失效
标题翻译：用于生产互连结构的保护硬掩模
公开(公告)号：US06720249B1
公开(公告)日：2004-04-13
申请号：US09550943
申请日：2000-04-17
申请人： Timothy J. Dalton , Christopher V. Jahnes , Joyce C. Liu , Sampath Purushothaman
发明人： Timothy J. Dalton , Christopher V. Jahnes , Joyce C. Liu , Sampath Purushothaman
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76802 , H01L21/76811 , H01L21/76813 , H01L21/76816 , H01L21/76829 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a permanent protective hardmask which protects the dielectric properties of a main dielectric layer having a desirably low dielectric constant in a semiconductor device from undesirable increases in the dielectric constant, undesirable increases in current leakage, and low device yield from surface scratching during subsequent processing steps. The protective hardmask further includes a single layer or dual layer sacrificial hardmask particularly useful when interconnect structures such as via openings and/or lines are formed in the low dielectric material during the course of making the final product. The sacrificial hardmask layers and the permanent hardmask layer may be formed in a single step from a same precursor wherein process conditions are altered to provide films of differing dielectric constants. Most preferably, a dual damascene structure has a tri-layer hardmask comprising silicon carbide BLoK™, PECVD silicon nitride, and PECVD silicon dioxide, respectively, formed over a bulk low dielectric constant interlevel dielectric prior to forming the interconnect structures in the interlevel dielectric.
摘要翻译：本发明提供一种永久性保护性硬掩模，其保护半导体器件中具有期望的低介电常数的主电介质层的介电性能，不需要介电常数的增加，不期望的电流泄漏增加，以及在表面划伤期间的低的器件产量后续处理步骤。保护性硬掩模还包括单层或双层牺牲硬掩模，在制造最终产品的过程中，在低电介质材料中形成诸如通孔开口和/或线之间的互连结构时尤其有用。牺牲硬掩模层和永久硬掩模层可以从相同的前体在单个步骤中形成，其中改变工艺条件以提供不同介电常数的膜。最优选地，双镶嵌结构具有三层硬掩模，其在形成层间的互连结构之前分别形成在体低介电常数层间电介质上的碳化硅BLoK TM，PECVD氮化硅和PECVD二氧化硅电介质。

5. 发明授权

US08940570B2 Micro-electro-mechanical system (MEMS) structures and design structures 有权
标题翻译：微机电系统（MEMS）结构和设计结构
公开(公告)号：US08940570B2
公开(公告)日：2015-01-27
申请号：US13342450
申请日：2012-01-03
申请人： Christopher V. Jahnes , Anthony K. Stamper
发明人： Christopher V. Jahnes , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： B81B3/001 , B81B3/0008 , B81B3/0013 , B81B2201/0221 , B81B2203/0109 , B81B2203/0118 , B81B2203/019 , B81C1/0015 , H01G5/18
摘要： Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one fixed electrode on a substrate. The method further includes forming a Micro-Electro-Mechanical System (MEMS) beam with a varying width dimension, as viewed from a top of the MEMS beam, over the at least one fixed electrode.
摘要翻译：公开了微机电系统（MEMS）结构，制造方法和设计结构。该方法包括在基板上形成至少一个固定电极。该方法还包括在至少一个固定电极上形成从MEMS光束的顶部观察的具有变化的宽度尺寸的微机电系统（MEMS）光束。

6. 发明授权

US08685778B2 Planar cavity MEMS and related structures, methods of manufacture and design structures 有权
标题翻译：平面腔MEMS及相关结构，制造方法和设计结构
公开(公告)号：US08685778B2
公开(公告)日：2014-04-01
申请号：US12973285
申请日：2010-12-20
申请人： Christopher V. Jahnes , Anthony K. Stamper
发明人： Christopher V. Jahnes , Anthony K. Stamper
IPC分类号： B81C1/00
CPC分类号： B81B3/0072 , B81B3/0021 , B81B2201/01 , B81B2201/014 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81C1/0015 , B81C1/00365 , B81C1/00476 , B81C1/00619 , B81C1/00626 , B81C1/00666 , B81C2201/0109 , B81C2201/013 , B81C2201/0167 , B81C2201/017 , B81C2203/0136 , B81C2203/0172 , G06F17/5068 , G06F17/5072 , H01H1/0036 , H01H57/00 , H01H59/0009 , H01H2057/006 , H01L41/1136 , H01L2924/0002 , Y10S438/937 , Y10T29/42 , Y10T29/435 , Y10T29/49002 , Y10T29/49105 , Y10T29/49121 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/5313 , H01L2924/00
摘要： A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a lower wiring layer. The method further includes forming a layer. The method further includes forming a second sacrificial cavity layer over the first sacrificial layer and in contact with the layer. The method further includes forming a lid on the second sacrificial cavity layer. The method further includes forming at least one vent hole in the lid, exposing a portion of the second sacrificial cavity layer. The method further includes venting or stripping the second sacrificial cavity layer such that a top surface of the second sacrificial cavity layer is no longer touching a bottom surface of the lid, before venting or stripping the first sacrificial cavity layer thereby forming a first cavity and second cavity, respectively.
摘要翻译：形成至少一个微机电系统（MEMS）腔的方法包括在下布线层上形成第一牺牲腔层。该方法还包括形成层。该方法还包括在第一牺牲层上形成与层接触的第二牺牲腔层。该方法还包括在第二牺牲腔层上形成盖子。该方法还包括在盖中形成至少一个通气孔，暴露第二牺牲腔层的一部分。该方法还包括排气或剥离第二牺牲腔层，使得第二牺牲腔层的顶表面在不排除或剥离第一牺牲腔层之前不再接触盖的底表面，从而形成第一腔和第二腔腔。

7. 发明申请

US20120273362A1 SURFACE CHARGE ENABLED NANOPOROUS SEMI-PERMEABLE MEMBRANE FOR DESALINATION 有权
标题翻译：用于脱盐的表面电荷使用的纳米半透膜
公开(公告)号：US20120273362A1
公开(公告)日：2012-11-01
申请号：US13534855
申请日：2012-06-27
申请人： John M. Cotte , Christopher V. Jahnes , Hongbo Peng , Stephen M. Rossnagel
发明人： John M. Cotte , Christopher V. Jahnes , Hongbo Peng , Stephen M. Rossnagel
IPC分类号： B03C9/00 , C25D5/02 , B82Y99/00 , B82Y40/00 , B82Y30/00
CPC分类号： B01D67/0065 , B01D71/022 , B01D2323/283 , B01D2325/021 , Y10T428/249953
摘要： A filter includes a membrane having a plurality of nanochannels formed therein. A first surface charge material is deposited on an end portion of the nanochannels. The first surface charge material includes a surface charge to electrostatically influence ions in an electrolytic solution such that the nanochannels reflect ions back into the electrolytic solution while passing a fluid of the electrolytic solution. Methods for making and using the filter are also provided.
摘要翻译：过滤器包括其中形成有多个纳米通道的膜。第一表面电荷材料沉积在纳米通道的端部上。第一表面电荷材料包括静电地影响电解溶液中的离子的表面电荷，使得纳米通道在通过电解液的流体时将离子反射回电解溶液。还提供了制造和使用过滤器的方法。

8. 发明申请

US20110094884A1 SURFACE CHARGE ENABLED NANOPOROUS SEMI-PERMEABLE MEMBRANE FOR DESALINATION 有权
标题翻译：用于脱盐的表面电荷使用的纳米半透膜
公开(公告)号：US20110094884A1
公开(公告)日：2011-04-28
申请号：US12607258
申请日：2009-10-28
申请人： John M. Cotte , Christopher V. Jahnes , Hongbo Peng , Stephen M. Rossnagel
发明人： John M. Cotte , Christopher V. Jahnes , Hongbo Peng , Stephen M. Rossnagel
IPC分类号： B01D61/42 , B01D61/46 , B01D61/54 , B01D67/00
CPC分类号： B01D67/0065 , B01D71/022 , B01D2323/283 , B01D2325/021 , Y10T428/249953
摘要： A filter includes a membrane having a plurality of nanochannels formed therein. A first surface charge material is deposited on an end portion of the nanochannels. The first surface charge material includes a surface charge to electrostatically influence ions in an electrolytic solution such that the nanochannels reflect ions back into the electrolytic solution while passing a fluid of the electrolytic solution. Methods for making and using the filter are also provided.
摘要翻译：过滤器包括其中形成有多个纳米通道的膜。第一表面电荷材料沉积在纳米通道的端部上。第一表面电荷材料包括静电地影响电解溶液中的离子的表面电荷，使得纳米通道在通过电解液的流体时将离子反射回电解溶液。还提供了制造和使用过滤器的方法。

9. 发明授权

US07417315B2 Negative thermal expansion system (NTEs) device for TCE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging 有权
标题翻译：负热膨胀系统（NTE）装置用于弹性体复合材料中的TCE补偿和微电子封装中的导电弹性体互连
公开(公告)号：US07417315B2
公开(公告)日：2008-08-26
申请号：US10310532
申请日：2002-12-05
申请人： Gareth Geoffrey Hougham , S. Jay Chey , James Patrick Doyle , Xiao Hu Liu , Christopher V. Jahnes , Paul Alfred Lauro , Nancy C. LaBianca , Michael J. Rooks
发明人： Gareth Geoffrey Hougham , S. Jay Chey , James Patrick Doyle , Xiao Hu Liu , Christopher V. Jahnes , Paul Alfred Lauro , Nancy C. LaBianca , Michael J. Rooks
IPC分类号： H01L21/302 , B32B5/22 , G02B26/00
CPC分类号： B81B3/0035 , H01L2924/0002 , Y10T428/249986 , H01L2924/00
摘要： A Negative Thermal Expansion system (NTEs) device for TCE compensation or CTE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging. One aspect of the present invention provides a method for fabricating micromachine devices that have negative thermal expansion coefficients that can be made into a composite for manipulation of the TCE of the material. These devices and composites made with these devices are in the categories of materials called “smart materials” or “responsive materials.” Another aspect of the present invention provides microdevices comprised of dual opposed bilayers of material where the two bilayers are attached to one another at the peripheral edges only, and where the bilayers themselves are at a minimum stress conditions at a reference temperature defined by the temperature at which the bilayers are formed. These devices have the technologically useful property of volumetrically expanding upon lowering of the device temperature below the reference or processing temperature.
摘要翻译：用于微电子封装中弹性体复合材料和导电弹性体互连的TCE补偿或CTE补偿的负热膨胀系统（NTE）装置。本发明的一个方面提供了一种用于制造具有负热膨胀系数的微机械装置的方法，该热膨胀系数可以制成用于操纵材料的TCE的复合材料。这些设备和这些设备制成的复合材料属于称为“智能材料”或“响应材料”的材料类别。本发明的另一方面提供了由双重相对的双层材料构成的微器件，其中两个双层仅在外围边缘处彼此附接，并且其中双层本身处于由温度定义的参考温度下的最小应力条件双层形成。当器件温度降低到参考温度或加工温度以下时，这些器件具有技术上有用的特性。

10. 发明授权

US06977569B2 Lateral microelectromechanical system switch 有权
公开(公告)号：US06977569B2
公开(公告)日：2005-12-20
申请号：US10915742
申请日：2004-08-11
申请人： Hariklia Deligianni , Christopher V. Jahnes , Jennifer L. Lund , Lawrence E. Larson
发明人： Hariklia Deligianni , Christopher V. Jahnes , Jennifer L. Lund , Lawrence E. Larson
IPC分类号： H01H59/00 , H01H51/22
CPC分类号： H01H59/0009 , H01H2001/0068 , H01H2001/0078
摘要： A switch comprising a substrate, an elongated movable part, a pair of electrical contacts disposed at one side of said part, an actuation electrode disposed at the one side of the part and separated from the pair of electrical contacts, wherein the part, the contacts and the electrode are disposed on the substrate, wherein the elongated movable part is arranged and dimensioned such that the part is movable in a generally lateral direction toward the contacts; the movable part includes a central elongated member fixed to a head having an electrical contact disposed at the one side. One end of the movable part is attached to the substrate by means of various anchoring arrangements.

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