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1. 发明授权

US06716742B2 Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics 有权
标题翻译：低k互连结构由多层旋涂多孔电介质组成
公开(公告)号：US06716742B2
公开(公告)日：2004-04-06
申请号：US10292205
申请日：2002-11-12
申请人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
发明人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76811 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.
摘要翻译：提供了其中不存在微沟槽的低k电介质金属导体互连结构以及形成这种结构的方法。具体地说，上述结构是通过提供一种互连结构来实现的，所述互连结构至少包括多层电介质材料，所述多层电介质材料依次应用于单个旋涂工具中，然后在单个步骤中固化，并且多个图案化的金属导体在多层纺丝 - 电介质。使用具有位于具有第一原子组成的多孔低k电介质的线路和通孔电介质层之间的第二原子组成的掩埋蚀刻停止层来获得对导体电阻的控制。本发明的互连结构还包括有助于形成双镶嵌型互连结构的硬掩模。选择第一和第二组合物以获得至少10至1或更高的蚀刻选择性，并且选自具有特定原子组成和其它可发现量的多孔低k有机或无机材料的特定组。

2. 发明授权

US06710450B2 Interconnect structure with precise conductor resistance and method to form same 有权
标题翻译：具有精确导体电阻的互连结构和形成相同的方法
公开(公告)号：US06710450B2
公开(公告)日：2004-03-23
申请号：US09795430
申请日：2001-02-28
申请人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
发明人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
IPC分类号： H01L23532
CPC分类号： H01L21/76835 , H01L21/02118 , H01L21/02126 , H01L21/02134 , H01L21/02137 , H01L21/022 , H01L21/02203 , H01L21/02282 , H01L21/3122 , H01L21/76811 , H01L21/7684
摘要： An interconnect structure including a patterned multilayer of spun-on dielectrics as well as methods for manufacturing the same are provided. The interconnect structure includes a patterned multilayer of spun-on dielectrics formed on a surface of a substrate. The patterned multilayer of spun-on dielectrics is composed of a bottom low-k dielectric, a buried etch stop layer, and a top low-k dielectric, wherein the bottom and top low-k dielectrics have a first composition, the said buried etch stop layer has a second composition which is different from the first composition and the buried etch stop layer is covalently bonded to said top and bottom low-k dielectrics. The interconnect structure further includes a polish stop layer formed on the patterned multilayer of spun-on dielectrics; and metal conductive regions formed within the patterned multilayer of spun-on dielectrics. Covalent bonding is achieved by employing an organosilane having functional groups that are capable of bonding with the top and bottom dielectric layers.
摘要翻译：提供了包括旋涂电介质的图案化多层的互连结构及其制造方法。互连结构包括形成在衬底的表面上的旋涂电介质的图案化多层。旋涂电介质的图案化多层由底部低k电介质，掩埋蚀刻停止层和顶部低k电介质组成，其中底部和顶部低k电介质具有第一组成，所述掩埋蚀刻停止层具有与第一组成不同的第二组成，并且掩埋蚀刻停止层共价键合到所述顶部和底部低k电介质。互连结构还包括形成在旋涂电介质的图案化多层上的抛光停止层; 以及形成在旋涂电介质的图案化多层中的金属导电区域。通过使用具有能够与顶部和底部电介质层结合的官能团的有机硅烷来实现共价键合。

3. 发明授权

US06603204B2 Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics 失效
公开(公告)号：US06603204B2
公开(公告)日：2003-08-05
申请号：US09795431
申请日：2001-02-28
申请人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
发明人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
IPC分类号： H01L2348
CPC分类号： H01L21/76835 , H01L21/76811 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.

4. 发明授权

US06831366B2 Interconnects containing first and second porous low-k dielectrics separated by a porous buried etch stop layer 有权
标题翻译：互连件包含由多孔掩埋蚀刻停止层隔开的第一和第二多孔低k电介质
公开(公告)号：US06831366B2
公开(公告)日：2004-12-14
申请号：US10396274
申请日：2003-03-25
申请人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
发明人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
IPC分类号： H01L2352
CPC分类号： H01L21/76835 , H01L21/76811 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.
摘要翻译：提供了其中不存在微沟槽的低k电介质金属导体互连结构以及形成这种结构的方法。具体地说，上述结构是通过提供一种互连结构来实现的，所述互连结构至少包括多层电介质材料，所述多层电介质材料依次应用于单个旋涂工具中，然后在单个步骤中固化，并且多个图案化的金属导体在多层纺丝 - 电介质。使用具有位于具有第一原子组成的多孔低k电介质的线路和通孔电介质层之间的第二原子组成的掩埋蚀刻停止层来获得对导体电阻的控制。本发明的互连结构还包括有助于形成双镶嵌型互连结构的硬掩模。选择第一和第二组合物以获得至少10至1或更高的蚀刻选择性，并且选自具有特定原子组成和其它可发现量的多孔低k有机或无机材料的特定组。

5. 发明授权

US06677680B2 Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials 有权
标题翻译：混合低k互连结构由2个旋涂电介质材料组成
公开(公告)号：US06677680B2
公开(公告)日：2004-01-13
申请号：US09795429
申请日：2001-02-28
申请人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
发明人： Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Cristy Sensenich Tyberg
IPC分类号： H01L2348
CPC分类号： H01L21/76835 , H01L21/02118 , H01L21/02126 , H01L21/022 , H01L21/02203 , H01L21/02282 , H01L21/3124 , H01L21/76811
摘要： A metal wiring plus low-k dielectric interconnect structure of the dual damascene-type is provided wherein the conductive metal lines and vias are built into a hybrid low-k dielectric which includes two spun-on dielectrics that have different atomic compositions and at least one of the two spun-on dielectrics is porous. The two spun-on dielectrics used in forming the inventive hybrid low-k dielectric each have a dielectric constant of about 2.6 or less, preferably each dielectric of the hybrid structure has a k of from about 1.2 to about 2.2. By utilizing the inventive hybrid low-k dielectric excellent control over metal line resistance (trench depth) is obtained, without no added cost. This is achieved without the use of a buried etch stop layer, which if present, would be formed between the two spun-on dielectrics. Moreover, the spun-on dielectrics of the hybrid low-k dielectric have distinctly different atomic compositions enabling control over the conductor resistance using the bottom spun-on dielectric (i.e., via dielectric) as an inherent etch stop layer for the upper spun-on dielectric (i.e., line dielectric).
摘要翻译：提供了一种双镶嵌型金属布线加上低k电介质互连结构，其中导电金属线和通孔内置于混合低k电介质中，该电介质包括两个具有不同原子组成的旋转电介质和至少一个的两个旋转电介质是多孔的。用于形成本发明的混合低k电介质的两个旋转电介质各自具有约2.6或更小的介电常数，优选混合结构的每个电介质具有约1.2至约2.2的k。通过利用本发明的混合低k电介质，获得对金属线电阻（沟槽深度）的优异控制，而不增加成本。这是在没有使用掩埋蚀刻停止层的情况下实现的，如果存在的话，它将在两个旋转电介质之间形成。此外，混合低k电介质的旋转电介质具有明显不同的原子组成，使得能够使用底部纺丝电介质（即，通过电介质）控制导体电阻，作为用于上纺丝的固有蚀刻停止层电介质（即线电介质）。

6. 发明授权

US06724069B2 Spin-on cap layer, and semiconductor device containing same 有权
标题翻译：旋转盖层，以及包含其的半导体器件
公开(公告)号：US06724069B2
公开(公告)日：2004-04-20
申请号：US09827160
申请日：2001-04-05
申请人： Timothy Joseph Dalton , Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Christy Sensenich Tyberg
发明人： Timothy Joseph Dalton , Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Christy Sensenich Tyberg
IPC分类号： H01L2358
CPC分类号： H01L21/76835 , H01L21/76801 , H01L21/76811 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A spin-on cap useful as a post-CMP cap for Cu interconnect structures is provided. The inventive spin-on cap includes a low-k dielectric (on the order of 3.5 or less) and at least one additive. The at least one additive employed in the present invention is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric. The spin-on cap of the present invention may further include a spun-on low-k (on the order of 3.5 or less) reactive-ion etch (RIE) stop layer. Spin-on caps containing a bilayer of low-dielectric plus at least additive and low-k RIE stop layer are preferred. It is noted that the inventive spin-on cap of the present invention does not significantly increase the effective dielectric constant of the interconnect structure and does not add additional cost to the fabrication of the interconnect structure since a single deposition tool, i.e., spin coating tool, is employed. Moreover, because of the presence of the additive in the spin-on cap, Cu migration is substantially minimized.
摘要翻译：提供了一种用作Cu互连结构的CMP后盖的旋涂帽。本发明的旋涂帽包括低k电介质（约3.5或更小）和至少一种添加剂。本发明中使用的至少一种添加剂能够结合Cu离子，并且可溶于旋转的低k电介质。本发明的旋涂帽还可以包括旋转低k（约3.5或更小）反应离子蚀刻（RIE）停止层。包含低电介质加上至少添加和低k RIE停止层的双层的旋转盖是优选的。注意，本发明的本发明的旋涂帽不会显着增加互连结构的有效介电常数，并且不会增加互连结构的制造的额外成本，因为单个沉积工具，即旋涂工具，被雇用。此外，由于在旋涂帽中存在添加剂，所以Cu迁移基本上被最小化。

7. 发明授权

US06537908B2 Method for dual-damascence patterning of low-k interconnects using spin-on distributed hardmask 失效
标题翻译：使用旋转分布式硬掩模的低k互连的双重磁阻图案化方法
公开(公告)号：US06537908B2
公开(公告)日：2003-03-25
申请号：US09795417
申请日：2001-02-28
申请人： Ann Rhea-Helene Fornof , Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Christy Sensenich Tyberg
发明人： Ann Rhea-Helene Fornof , Stephen McConnell Gates , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Christy Sensenich Tyberg
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/31058 , H01L21/31144 , H01L21/76811
摘要： A cost effective and simple method of patterning interconnect structures is provided in which spun-on materials are used as the hard mask. The use of spun-on materials for the hard mask ensures that the process is carried out in a single tool and it permits the use of a single curing step which is not typically employed in patterning processes wherein CVD hard masks are employed. The effective dielectric constant of the resultant structure is not significantly increased since the use of spin coating allows for selection of a polish stop layer (formed on a surface of a low-k dielectric) that has substantially the same dielectric constant as the underlying dielectric. In the present invention, the hard mask employed includes at least two spun-on dielectric materials that have different etch rates.
摘要翻译：提供了一种成本有效和简单的图案互连结构的方法，其中使用旋转材料作为硬掩模。用于硬掩模的旋涂材料的使用确保了该工艺在单个工具中进行，并且其允许使用单一的固化步骤，其通常不用于使用CVD硬掩模的图案化工艺中。所得结构的有效介电常数不会显着增加，因为使用旋涂可以选择与下面的电介质基本相同的介电常数的抛光停止层（形成在低k电介质的表面上）。在本发明中，所用的硬掩模包括具有不同蚀刻速率的至少两个旋涂介电材料。

8. 发明授权

US06831364B2 Method for forming a porous dielectric material layer in a semiconductor device and device formed 有权
标题翻译：在半导体器件中形成多孔介电材料层的方法和形成的器件
公开(公告)号：US06831364B2
公开(公告)日：2004-12-14
申请号：US10210173
申请日：2002-08-01
申请人： Timothy Joseph Dalton , Stephen Edward Greco , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Kenneth Parker Rodbell , Robert Rosenberg
发明人： Timothy Joseph Dalton , Stephen Edward Greco , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Kenneth Parker Rodbell , Robert Rosenberg
IPC分类号： H01L2352
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02362 , H01L21/31695 , H01L21/76802 , H01L21/7682 , H01L21/76828 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus forming a dielectric material that has a low dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.
摘要翻译：公开了一种在电子结构中形成多孔介电材料层的方法和形成的结构。在该方法中，半导体器件中的多孔电介质层可以通过首先形成无孔介电层，然后通过反应离子蚀刻进行部分固化，图案化，并且在比无孔介电层更高的温度下最终固化无孔介电层部分固化温度以将无孔电介质材料转变为多孔电介质材料，从而形成具有低介电常数（即小于2.6）的电介质材料。无孔介电材料可以通过将热稳定的介电材料如甲基倍半硅氧烷，氢倍半硅氧烷，苯并环丁烯或芳族热固性聚合物与其中的第二相聚合物材料嵌入而形成，使得在较高固化温度下，第二相聚合物材料基本上挥发以在形成空隙填充的电介质材料之后留下空隙。

9. 发明授权

US06451712B1 Method for forming a porous dielectric material layer in a semiconductor device and device formed 有权
标题翻译：在半导体器件中形成多孔介电材料层的方法和形成的器件
公开(公告)号：US06451712B1
公开(公告)日：2002-09-17
申请号：US09739935
申请日：2000-12-18
申请人： Timothy Joseph Dalton , Stephen Edward Greco , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Kenneth Parker Rodbell , Robert Rosenberg
发明人： Timothy Joseph Dalton , Stephen Edward Greco , Jeffrey Curtis Hedrick , Satyanarayana V. Nitta , Sampath Purushothaman , Kenneth Parker Rodbell , Robert Rosenberg
IPC分类号： H01L2131
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02362 , H01L21/31695 , H01L21/76802 , H01L21/7682 , H01L21/76828 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus achieving a dielectric material that has significantly improved dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.
摘要翻译：公开了一种在电子结构中形成多孔介电材料层的方法和形成的结构。在该方法中，半导体器件中的多孔电介质层可以通过首先形成无孔介电层，然后通过反应离子蚀刻进行部分固化，图案化，并且在比无孔介电层更高的温度下最终固化无孔介电层部分固化温度以将无孔电介质材料转化为多孔电介质材料，从而获得具有显着改善介电常数（即小于2.6）的电介质材料。无孔介电材料可以通过将热稳定的介电材料如甲基倍半硅氧烷，氢倍半硅氧烷，苯并环丁烯或芳族热固性聚合物与其中的第二相聚合物材料嵌入而形成，使得在较高的固化温度下，第二相聚合物材料基本上挥发以在形成空隙填充的电介质材料之后留下空隙。

10. 发明授权

US06737725B2 Multilevel interconnect structure containing air gaps and method for making 有权
标题翻译：包含气隙的多层互连结构和制造方法
公开(公告)号：US06737725B2
公开(公告)日：2004-05-18
申请号：US10144574
申请日：2002-05-13
申请人： Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Satyanarayana Venkata Nitta , Kevin S. Petrarca , Sampath Purushothaman , Katherine Lynn Saenger , Stanley Joseph Whitehair
发明人： Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Satyanarayana Venkata Nitta , Kevin S. Petrarca , Sampath Purushothaman , Katherine Lynn Saenger , Stanley Joseph Whitehair
IPC分类号： H01L2900
CPC分类号： H01L21/7682 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L21/76885
摘要： A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics. The inventive method includes the steps of: (a) forming a first planar via plus line level pair embedded in a dielectric matrix formed from one or more solid dielectrics and comprising a via level dielectric and a line level dielectric on a substrate, wherein, at least one of said solid dielectrics is at least partially sacrificial; (b) etching back sacrificial portions of said at least partially sacrificial dielectrics are removed to leave cavities extending into and through said via level, while leaving, at least some of the original via level dielectric as a permanent dielectric under said lines; (c) partially filling or overfilling said cavities with a place-holder material which may or may not be sacrificial; (d) planarizing the structure by removing overfill of said place-holder material; (e) repeating, as necessary, steps (a)-(d); (f) forming a dielectric bridge layer over the planar structure; and (g) forming air gaps by at least partially extracting said place-holder material.
摘要翻译：一种在衬底上形成多层互连结构的方法，其包括互连的导电布线和通过固体或气体电介质的组合间隔开的通孔。本发明的方法包括以下步骤：（a）形成嵌入在由一个或多个固体电介质形成的电介质矩阵中并且包括通孔层电介质和衬底上的线路电介质的介电矩阵中的第一平面通孔加线电平对，其中，在至少一个所述固体电介质至少部分地是牺牲的; （b）蚀刻所述至少部分牺牲电介质的牺牲部分被去除以留下延伸进入并穿过所述通孔级的空腔，同时留下至少一些原始通孔级电介质作为所述线下的永久电介质; （c）用可能牺牲或可能不是牺牲的位置保持材料部分填充或过度填充所述空腔; （d）通过去除所述位置保持器材料的过量填充来平坦化结构; （e）必要时重复步骤（a） - （d）; （f）在所述平面结构上形成电介质桥接层; 和（g）通过至少部分地提取所述放置支架材料形成气隙。

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