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1. 发明申请

US20090239354A1 METHOD FOR MANUFACTURING SOI SUBSTRATE 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US20090239354A1
公开(公告)日：2009-09-24
申请号：US12399047
申请日：2009-03-06
申请人： Hideomi SUZAWA , Shinya SASAGAWA , Akihisa SHIMOMURA , Junpei MOMO , Motomu KURATA , Taiga MURAOKA , Kosei NEI
发明人： Hideomi SUZAWA , Shinya SASAGAWA , Akihisa SHIMOMURA , Junpei MOMO , Motomu KURATA , Taiga MURAOKA , Kosei NEI
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light.
摘要翻译：在单晶半导体基板的表面上形成绝缘膜，在单晶半导体基板中通过用离子束照射单晶半导体基板通过绝缘膜形成脆性区域，在绝缘膜上形成接合层，通过将支撑基板和单晶半导体基板之间的接合层插入到单晶半导体基板的支撑基板上，将单晶半导体基板分割为脆性区域，将单晶半导体基板分离成单晶半导体层，所述支撑基板对残留在所述单晶半导体层上的所述脆性区域的一部分进行第一干蚀刻处理，对经过所述第一蚀刻处理的所述单晶半导体层的表面进行第二干蚀刻处理，具有激光的晶体半导体层。

2. 发明申请

US20110287605A1 METHOD FOR MANUFACTURING SOI SUBSTRATE 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US20110287605A1
公开(公告)日：2011-11-24
申请号：US13198171
申请日：2011-08-04
申请人： Hideomi SUZAWA , Shinya SASAGAWA , Akihisa SHIMOMURA , Junpei MOMO , Motomu KURATA , Taiga MURAOKA , Kosei NEI
发明人： Hideomi SUZAWA , Shinya SASAGAWA , Akihisa SHIMOMURA , Junpei MOMO , Motomu KURATA , Taiga MURAOKA , Kosei NEI
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light.
摘要翻译：在单晶半导体基板的表面上形成绝缘膜，在单晶半导体基板中通过用离子束照射单晶半导体基板通过绝缘膜形成脆性区域，在绝缘膜上形成接合层，通过将支撑基板和单晶半导体基板之间的接合层插入到单晶半导体基板的支撑基板上，将单晶半导体基板分割为脆性区域，将单晶半导体基板分离成单晶半导体层，所述支撑基板对残留在所述单晶半导体层上的所述脆性区域的一部分进行第一干蚀刻处理，对经过所述第一蚀刻处理的所述单晶半导体层的表面进行第二干蚀刻处理，具有激光的晶体半导体层。

3. 发明申请

US20110117698A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110117698A1
公开(公告)日：2011-05-19
申请号：US13012987
申请日：2011-01-25
申请人： Hideomi SUZAWA , Shinya SASAGAWA , Taiga MURAOKA
发明人： Hideomi SUZAWA , Shinya SASAGAWA , Taiga MURAOKA
IPC分类号： H01L21/465
CPC分类号： H01L27/127 , G02F1/134309 , G02F1/136227 , G02F1/167 , G09F21/04 , G09G3/3648 , G09G3/3677 , G09G2300/0408 , G09G2300/0809 , G09G2310/0251 , G09G2310/0286 , G09G2310/08 , G11C19/28 , H01L21/465 , H01L27/1225 , H01L27/124 , H01L27/3262 , H01L29/66969 , H01L29/7869 , H01L29/78696
摘要： An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.
摘要翻译：本发明的目的是建立一种其中使用氧化物半导体的半导体器件的制造中的加工技术。在基板上形成栅电极，在栅电极上形成栅极绝缘层，在栅极绝缘层上形成氧化物半导体层，通过湿蚀刻加工氧化物半导体层，形成岛状氧化物半导体层形成导电层以覆盖岛状氧化物半导体层，通过干蚀刻处理导电层以形成源电极，并且通过干蚀刻除去漏电极和岛状氧化物半导体层的一部分，在岛状氧化物半导体层中形成凹部。

4. 发明申请

US20100105162A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100105162A1
公开(公告)日：2010-04-29
申请号：US12582074
申请日：2009-10-20
申请人： Hideomi SUZAWA , Shinya SASAGAWA , Taiga MURAOKA
发明人： Hideomi SUZAWA , Shinya SASAGAWA , Taiga MURAOKA
IPC分类号： H01L21/336 , H01L21/34
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1225 , H01L29/7869
摘要： In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. The etching step is performed by dry etching in which an etching gas is used.
摘要翻译：在制造包括通道蚀刻反交错薄膜晶体管的半导体器件的方法中，使用使用作为曝光的多色调掩模形成的掩模层来蚀刻氧化物半导体膜和导电膜光透过该掩模以具有多个强度。蚀刻步骤通过使用蚀刻气体的干蚀刻进行。

5. 发明申请

US20100099216A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100099216A1
公开(公告)日：2010-04-22
申请号：US12580512
申请日：2009-10-16
申请人： Hideomi SUZAWA , Shinya SASAGAWA , Taiga MURAOKA
发明人： Hideomi SUZAWA , Shinya SASAGAWA , Taiga MURAOKA
IPC分类号： H01L21/336
CPC分类号： H01L27/127 , G02F1/134309 , G02F1/136227 , G02F1/167 , G09F21/04 , G09G3/3648 , G09G3/3677 , G09G2300/0408 , G09G2300/0809 , G09G2310/0251 , G09G2310/0286 , G09G2310/08 , G11C19/28 , H01L21/465 , H01L27/1225 , H01L27/124 , H01L27/3262 , H01L29/66969 , H01L29/7869 , H01L29/78696
摘要： An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.
摘要翻译：本发明的目的是建立一种其中使用氧化物半导体的半导体器件的制造中的加工技术。在基板上形成栅电极，在栅电极上形成栅极绝缘层，在栅极绝缘层上形成氧化物半导体层，通过湿蚀刻加工氧化物半导体层，形成岛状氧化物半导体层形成导电层以覆盖岛状氧化物半导体层，通过干蚀刻处理导电层以形成源电极，并且通过干蚀刻除去漏电极和岛状氧化物半导体层的一部分，在岛状氧化物半导体层中形成凹部。

6. 发明申请

US20120286266A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120286266A1
公开(公告)日：2012-11-15
申请号：US13555579
申请日：2012-07-23
申请人： Hideomi SUZAWA , Shinya SASAGAWA , Taiga MURAOKA , Shunichi ITO , Miyuki HOSOBA
发明人： Hideomi SUZAWA , Shinya SASAGAWA , Taiga MURAOKA , Shunichi ITO , Miyuki HOSOBA
IPC分类号： H01L29/26
CPC分类号： H01L29/66969 , H01L27/1225 , H01L27/1288 , H01L29/66742 , H01L29/78621 , H01L29/7869
摘要： An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.
摘要翻译：本发明的目的是以低成本，高生产率制造包括氧化物半导体的半导体器件，使得通过减少曝光掩模的数量来简化光刻工艺。在包括通道蚀刻的半导体器件的制造方法中倒置交错薄膜晶体管，氧化物半导体膜和导电膜使用掩模层进行蚀刻，该掩模层使用作为透光的多色调掩模形成，该透光掩模通过该曝光掩模透射，以便具有多个强度在蚀刻步骤中，通过使用蚀刻剂的湿式蚀刻进行第一蚀刻步骤，并且通过使用蚀刻气体的干法蚀刻进行第二蚀刻步骤。

7. 发明申请

US20100283105A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100283105A1
公开(公告)日：2010-11-11
申请号：US12840442
申请日：2010-07-21
申请人： Shunpei YAMAZAKI , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA
发明人： Shunpei YAMAZAKI , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA
IPC分类号： H01L29/786
CPC分类号： H01L29/41733 , H01L21/76804 , H01L21/76805 , H01L23/485 , H01L27/124 , H01L2924/0002 , H01L2924/00
摘要： A technique of manufacturing a semiconductor device in which etching in formation of a contact hole can be easily controlled is proposed. A semiconductor device includes at least a semiconductor layer formed over an insulating surface; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; and a conductive layer formed over the second insulating layer connected to the semiconductor layer via an opening which is formed at least in the semiconductor layer and the second insulating layer and partially exposes the insulating surface. The conductive layer is electrically connected to the semiconductor layer at the side surface of the opening which is formed in the semiconductor layer.
摘要翻译：提出了可以容易地控制形成接触孔的蚀刻的半导体器件的制造技术。半导体器件至少包括形成在绝缘表面上的半导体层; 形成在所述半导体层上的第一绝缘层; 形成在所述第一绝缘层上的栅电极; 形成在所述栅电极上的第二绝缘层; 以及形成在所述第二绝缘层之上的导电层，所述导电层经由至少在所述半导体层和所述第二绝缘层中形成并且部分地暴露所述绝缘表面的开口连接到所述半导体层。导电层在形成于半导体层的开口的侧面与半导体层电连接。

8. 发明申请

US20110193080A1 Semiconductor device and electronic appliance 有权
标题翻译：半导体器件和电子设备
公开(公告)号：US20110193080A1
公开(公告)日：2011-08-11
申请号：US13014081
申请日：2011-01-26
申请人： Shunpei YAMAZAKI , Hiromichi GODO , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA , Mayumi MIKAMI
发明人： Shunpei YAMAZAKI , Hiromichi GODO , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA , Mayumi MIKAMI
IPC分类号： H01L29/78
CPC分类号： H01L29/7869 , H01L29/41733 , H01L29/45 , H01L29/66969 , Y10T428/24421
摘要： One object is to provide a semiconductor device that includes an oxide semiconductor and is reduced in size with favorable characteristics maintained. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The source electrode or the drain electrode includes a first conductive layer and a second conductive layer having a region extended in a channel length direction from an end face of the first conductive layer. The sidewall insulating layer has a length of a bottom surface in the channel length direction smaller than a length in the channel length direction of the extended region of the second conductive layer and is provided over the extended region.
摘要翻译：一个目的是提供一种包括氧化物半导体的半导体器件，并且尺寸减小，并保持良好的特性。半导体器件包括与氧化物半导体层接触的氧化物半导体层，源电极和漏电极，与氧化物半导体层重叠的栅电极; 以及在氧化物半导体层和栅电极之间的栅极绝缘层。源电极或漏极包括第一导电层和具有从第一导电层的端面在沟道长度方向上延伸的区域的第二导电层。侧壁绝缘层的沟道长度方向的底面的长度小于第二导电层的延伸区域的沟道长度方向的长度，并且设置在延伸区域上。

9. 发明申请

US20110180796A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110180796A1
公开(公告)日：2011-07-28
申请号：US13008285
申请日：2011-01-18
申请人： Shunpei YAMAZAKI , Hiromichi GODO , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA , Mayumi MIKAMI
发明人： Shunpei YAMAZAKI , Hiromichi GODO , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA , Mayumi MIKAMI
IPC分类号： H01L29/24
CPC分类号： H01L29/7869
摘要： An object is to provide a semiconductor device including an oxide semiconductor, which maintains favorable characteristics and achieves miniaturization. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, in which the source electrode and the drain electrode each include a first conductive layer, and a second conductive layer having a region which extends in a channel length direction from an end portion of the first conductive layer.
摘要翻译：本发明的目的是提供一种包含氧化物半导体的半导体器件，其保持有利的特性并实现小型化。半导体器件包括与氧化物半导体层接触的氧化物半导体层，源极和漏电极，与氧化物半导体层重叠的栅电极，以及设置在氧化物半导体层和栅电极之间的栅极绝缘层，其中源电极和漏极各自包括第一导电层，以及具有从第一导电层的端部在沟道长度方向上延伸的区域的第二导电层。

10. 发明申请

US20120286267A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120286267A1
公开(公告)日：2012-11-15
申请号：US13557719
申请日：2012-07-25
申请人： Hideomi SUZAWA , Shinya SASAGAWA , Taiga MURAOKA
发明人： Hideomi SUZAWA , Shinya SASAGAWA , Taiga MURAOKA
IPC分类号： H01L33/08
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1225 , H01L29/7869
摘要： In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. The etching step is performed by dry etching in which an etching gas is used.
摘要翻译：在制造包括通道蚀刻反交错薄膜晶体管的半导体器件的方法中，使用使用作为曝光的多色调掩模形成的掩模层来蚀刻氧化物半导体膜和导电膜光透过该掩模以具有多个强度。蚀刻步骤通过使用蚀刻气体的干蚀刻进行。

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