专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07596734B2 On-Chip AC self-test controller 有权
标题翻译：片上AC自检控制器
公开(公告)号：US07596734B2
公开(公告)日：2009-09-29
申请号：US12185172
申请日：2008-08-04
申请人： John D. Flanagan , Jay R. Herring , Tin-Chee Lo
发明人： John D. Flanagan , Jay R. Herring , Tin-Chee Lo
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G01R31/2891 , G01R31/31922
摘要： A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation is provided. The system includes the system clock, self-test circuitry, a first and second test register to capture and launch test data in response to a sequence of data pulses, and a logic circuit to be tested. The self-test circuitry includes an AC self-test controller and a clock splitter. The clock splitter generates the sequence of data pulses including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse. The at speed data launch pulse and the at speed data capture pulse are generated for a common cycle of the system clock.
摘要翻译：提供了一种用于在包括用于正常操作的系统时钟的集成电路上执行AC自检的系统。该系统包括系统时钟，自检电路，第一和第二测试寄存器，用于响应于数据脉冲序列捕获和发射测试数据，以及待测试的逻辑电路。自检电路包括一个交流自检控制器和时钟分离器。时钟分配器产生数据脉冲序列，包括长数据捕获脉冲，随后是速度数据发射脉冲和速度数据捕获脉冲，随后是长数据发射脉冲。为系统时钟的公共周期产生速度数据发射脉冲和速度数据捕获脉冲。

2. 发明申请

US20070240021A1 METHOD, SYSTEM AND PROGRAM PRODUCT FOR AUTONOMOUS ERROR RECOVERY FOR MEMORY DEVICES 失效
标题翻译：用于存储器件自动错误恢复的方法，系统和程序产品
公开(公告)号：US20070240021A1
公开(公告)日：2007-10-11
申请号：US11763653
申请日：2007-06-15
申请人： Sandeep Brahmadathan , Tin-Chee Lo , Jeffrey Turner
发明人： Sandeep Brahmadathan , Tin-Chee Lo , Jeffrey Turner
IPC分类号： G01R31/28
CPC分类号： G06F11/1032 , G06F12/0802
摘要： An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addressed storage compartment of a second memory device are automatically retrieved and provided responsive to the request. As an example, the memory device may be a cache and the second memory device may be main memory for the computing system.
摘要翻译：为计算系统的存储器件提供自主的错误恢复方法。响应于对数据的请求，测试存储器设备的寻址数据和相关控制信息的错误。如果检测到错误，则响应于该请求，自动地检索并提供第二存储设备的寻址存储隔间的内容。作为示例，存储器设备可以是高速缓存，并且第二存储器设备可以是计算系统的主存储器。

3. 发明授权

US07275202B2 Method, system and program product for autonomous error recovery for memory devices 有权
标题翻译：用于存储设备自主性错误恢复的方法，系统和程序产品
公开(公告)号：US07275202B2
公开(公告)日：2007-09-25
申请号：US10820178
申请日：2004-04-07
申请人： Sandeep Brahmadathan , Tin-chee Lo , Jeffrey M. Turner
发明人： Sandeep Brahmadathan , Tin-chee Lo , Jeffrey M. Turner
IPC分类号： H03M13/00
CPC分类号： G06F11/1032 , G06F12/0802
摘要： An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addressed storage compartment of a second memory device are automatically retrieved and provided responsive to the request. As an example, the memory device may be a cache and the second memory device may be main memory for the computing system.
摘要翻译：为计算系统的存储器件提供自主的错误恢复方法。响应于对数据的请求，测试存储器设备的寻址数据和相关控制信息的错误。如果检测到错误，则响应于该请求，自动地检索并提供第二存储设备的寻址存储隔间的内容。作为示例，存储器设备可以是高速缓存，并且第二存储器设备可以是计算系统的主存储器。

4. 发明申请

US20060242509A1 Method and system for an on-chip AC self-test controller 有权
公开(公告)号：US20060242509A1
公开(公告)日：2006-10-26
申请号：US11323449
申请日：2005-12-30
申请人： John Flanagan , Jay Herring , Tin-Chee Lo
发明人： John Flanagan , Jay Herring , Tin-Chee Lo
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G01R31/2891 , G01R31/31922
摘要： An exemplary embodiment of the present invention is a method for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation. The method comprises applying a long data capture pulse to a first test register in response to said system clock. An at speed data launch pulse is applied to the first test register in response to said system clock. The data from the first register is input to a logic path in response to applying the at speed data launch pulse to the first test register. An at speed data capture pulse is applied to a second test register in response to the system clock. The output from the logic path is input to the second test register in response to applying the at speed data capture pulse to the second test register. A long data launch pulse is applied to the second test register in response to the system clock. An additional embodiment includes a system for performing AC self-test on an integrated circuit that includes a system clock.

5. 发明授权

US5359722A Method for shortening memory fetch time relative to memory store time and controlling recovery in a DRAM 失效
标题翻译：相对于存储器存储时间缩短存储器获取时间并控制DRAM中的恢复的方法
公开(公告)号：US5359722A
公开(公告)日：1994-10-25
申请号：US555960
申请日：1990-07-23
申请人： Shiu K. Chan , Joseph H. Datres, Jr. , Tin-Chee Lo
发明人： Shiu K. Chan , Joseph H. Datres, Jr. , Tin-Chee Lo
IPC分类号： G06F12/06 , G06F12/08 , G11C7/22 , G11C11/401 , G11C11/4076 , G11C29/00 , G11C29/42 , G06F12/00 , G06F1/04
CPC分类号： G11C7/22 , G11C11/4076
摘要： A method for reducing fetch time in a computer system provides a memory fetch cycle that is shorter than the memory store cycle. Each chip of the computer system has at least one dynamic random access memory array (DRAM) and a small high speed cache static random access memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and recovery in the DRAM. The RAS starts DRAM recovery for a fetch cycle at or near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that control DRAM recovery while fetching during DRAM data from the SRAMs, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.
摘要翻译：用于减少计算机系统中的获取时间的方法提供比存储器存储周期短的存储器获取周期。计算机系统的每个芯片在芯片上具有至少一个动态随机存取存储器阵列（DRAM）和小型高速缓存静态随机存取存储器（SRAM）。系统存储器控制器在生成DRAM子地址定时信号（RAS）和高速缓存地址定时信号（CAS）时识别存储器请求的获取或存储状态，用于实现SRAM中的位的访问和寻址以及在SRAM中的恢复 DRAM。在从芯片上的SRAM提取数据开始或接近开始的时候，RAS启动DRAM恢复，但是控制RAS在存储周期之前不开始DRAM恢复，直到完成SRAM数据存储。芯片上的时钟包含控制DRAM恢复的电路，在DRAM的DRAM数据期间提取DRAM，但是防止DRAM恢复开始直到SRAM中的数据存储完成。

6. 发明授权

US5058115A Fault tolerant computer memory systems and components employing dual level error correction and detection with lock-up feature 失效
标题翻译：故障容错计算机存储系统和组件采用双层错误校正和锁定功能检测
公开(公告)号：US5058115A
公开(公告)日：1991-10-15
申请号：US322255
申请日：1989-03-10
申请人： Robert M. Blake , Douglas C. Bossen , Chin-Long Chen , John A. Fifield , Howard L. Kalter , Tin-Chee Lo
发明人： Robert M. Blake , Douglas C. Bossen , Chin-Long Chen , John A. Fifield , Howard L. Kalter , Tin-Chee Lo
IPC分类号： G06F12/16 , G06F11/10
CPC分类号： G06F11/1052 , G06F11/1008
摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, clip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

7. 发明授权

US06910165B2 Digital random noise generator 失效
标题翻译：数字随机噪声发生器
公开(公告)号：US06910165B2
公开(公告)日：2005-06-21
申请号：US09795899
申请日：2001-02-28
申请人： Howard H. Chen , Li-Kong Wang , Louis L. Hsu , Sang H. Dhong , Tin-chee Lo
发明人： Howard H. Chen , Li-Kong Wang , Louis L. Hsu , Sang H. Dhong , Tin-chee Lo
IPC分类号： G01R31/28 , H03K3/84 , G06F11/00
CPC分类号： H03K3/84 , G01R31/2841
摘要： A system and method for generating random noise for use in testing electronic devices comprises a first random pattern generator circuit for generating first sets of random bit pattern signals; one or more delay devices each receiving a trigger input signal and a random bit pattern signal set for generating in response a respective delay output signal, each delay output signal being delayed in time with respect to a respective trigger signal, a delay time being determined by the bit pattern set received; and, an oscillator circuit device associated with a respective one or more delay devices for receiving a respective delay output signal therefrom and generating a respective oscillating signal, each oscillator signal generated being used to generate artificial random noise for emulating a real noise environment in an electronic device. A second random pattern generator circuit may be provided for generating second sets of random bit pattern signals for receipt by each of the associated oscillator circuit devices in order to frequency adjust in a random manner, each of the oscillator signals.
摘要翻译：用于产生用于测试电子设备的随机噪声的系统和方法包括：第一随机模式发生器电路，用于产生第一组随机位模式信号; 每个接收触发输入信号的一个或多个延迟装置和随机位模式信号组，用于响应于相应的延迟输出信号而产生，每个延迟输出信号相对于相应的触发信号在时间上延迟，延迟时间由接收到位模式集; 以及与相应的一个或多个延迟装置相关联的振荡器电路装置，用于从其接收相应的延迟输出信号并产生相应的振荡信号，所产生的每个振荡器信号用于产生人造随机噪声，以仿真电子中的实际噪声环境设备。可以提供第二随机模式发生器电路，用于产生第二组随机位模式信号，以便由每个相关联的振荡器电路装置接收，以便随机地调整每个振荡器信号。

8. 发明授权

US06836840B2 Slaves with identification and selection stages for group write 失效
标题翻译：具有组写入识别和选择阶段的从站
公开(公告)号：US06836840B2
公开(公告)日：2004-12-28
申请号：US09918189
申请日：2001-07-30
申请人： Tin-chee Lo , Yuk-Ming Ng , Anil S. Keste
发明人： Tin-chee Lo , Yuk-Ming Ng , Anil S. Keste
IPC分类号： G06F1516
CPC分类号： G06F15/78
摘要： A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.
摘要翻译：一种使用组写入从机和包括识别级的序列对准逻辑模块的设计和方法，所述识别级具有第一ID输入，第二ID输入，ID与门和ID比较器，选择级，选择级，具有第一选择输入端口，组写入比较器，单独选择比较器，或门和选择与门，从模块，其中从模块包括组等待信号和组后位信号和序列对准逻辑模块，其包括具有逻辑电路的门控逻辑部分，逻辑电路被构造为通过排序和组合多个序列比对逻辑模块输入信号来创建序列比对逻辑模块输出信号，以便表示序列比对逻辑模块输入信号中最慢的。

9. 发明授权

US06594196B2 Multi-port memory device and system for addressing the multi-port memory device 失效
公开(公告)号：US06594196B2
公开(公告)日：2003-07-15
申请号：US09725967
申请日：2000-11-29
申请人： Louis L Hsu , Tin-chee Lo , Li-Kong Wang
发明人： Louis L Hsu , Tin-chee Lo , Li-Kong Wang
IPC分类号： G11C800
CPC分类号： G06F13/18 , G11C7/1075 , G11C8/16 , G11C11/405
摘要： A multi-port memory array is associated with wordlines and bit-lines to perform data read/write operation and has multi-port memory cells each of which includes multiple ports through which the wordlines and bit-lines are provided, multiple transistor devices each of which corresponds to each of the multiple ports and is coupled to a wordline and a bit-line through a corresponding port, each transistor device being gated by a wordline and having a conduction path of which a first end is connected to a bit-line, and a charge storage device commonly connected to a second end of a conduction path of each of the transistor devices, where the charge storage device is charged when any of the plurality of transistor devices is activated. A system for addressing the multi-port memory array includes a conflict detector for detecting a conflict between two or more of the row address signals to generate a conflict control signal corresponding to the conflict detected, a priority logic circuit for performing a logic operation with respect to the request command signals based on a predetermined priority logic to generate prioritized signals, and a selection unit for selecting one of a request command signal and a prioritized signal corresponding to the request command signal in response to the conflict control signal, where a signal selected by the selection unit selects a corresponding one of the row address signals.

10. 发明授权

US5822338A ECC-compare path of cache directory logic improvements 失效
标题翻译： ECC比较缓存目录逻辑改进路径
公开(公告)号：US5822338A
公开(公告)日：1998-10-13
申请号：US14503
申请日：1998-01-28
申请人： Tin-Chee Lo
发明人： Tin-Chee Lo
IPC分类号： G06F11/10 , G06F11/00
CPC分类号： G06F11/1064
摘要： Directory compare and ECC logic which is interfaced with the array's static and dynamic outputs for the ECC-compare path of a cache directory, using a three-output array providing a static output and a pair of complementary dynamic outputs. The static output is useed by the compare logic for a directory compare. The pair of complementary dynamic outputs provide dynamic signals (t and f) to drive the ECC logic only as ECC logic complementary signals which are coupled to drive a DCVS (Dynamic Cascode Voltage Switch) syndrome generator circuit. The static output signal performs compare-then-correct processing. The dynamic signals of each bit emanating from array are ECC checked but the static signal is not. The static signal is consistent with the t dynamic signal.
摘要翻译：目录比较和ECC逻辑，其与阵列的静态和动态输出接口，用于缓存目录的ECC比较路径，使用提供静态输出的三输出阵列和一对互补的动态输出。静态输出由目录比较的比较逻辑使用。这对互补动态输出提供动态信号（t和f），以驱动ECC逻辑，仅作为耦合到驱动DCVS（动态串联电压开关）校正子发生器电路的ECC逻辑互补信号。静态输出信号执行比较然后正确的处理。从阵列发出的每个位的动态信号被检查，但是静态信号不是。静态信号与t动态信号一致。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式