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1. 发明授权

US07275202B2 Method, system and program product for autonomous error recovery for memory devices 有权
标题翻译：用于存储设备自主性错误恢复的方法，系统和程序产品
公开(公告)号：US07275202B2
公开(公告)日：2007-09-25
申请号：US10820178
申请日：2004-04-07
申请人： Sandeep Brahmadathan , Tin-chee Lo , Jeffrey M. Turner
发明人： Sandeep Brahmadathan , Tin-chee Lo , Jeffrey M. Turner
IPC分类号： H03M13/00
CPC分类号： G06F11/1032 , G06F12/0802
摘要： An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addressed storage compartment of a second memory device are automatically retrieved and provided responsive to the request. As an example, the memory device may be a cache and the second memory device may be main memory for the computing system.
摘要翻译：为计算系统的存储器件提供自主的错误恢复方法。响应于对数据的请求，测试存储器设备的寻址数据和相关控制信息的错误。如果检测到错误，则响应于该请求，自动地检索并提供第二存储设备的寻址存储隔间的内容。作为示例，存储器设备可以是高速缓存，并且第二存储器设备可以是计算系统的主存储器。

2. 发明申请

US20050229052A1 Method, system and program product for autonomous error recovery for memory devices 有权
标题翻译：用于存储设备自主性错误恢复的方法，系统和程序产品
公开(公告)号：US20050229052A1
公开(公告)日：2005-10-13
申请号：US10820178
申请日：2004-04-07
申请人： Sandeep Brahmadathan , Tin-chee Lo , Jeffrey Turner
发明人： Sandeep Brahmadathan , Tin-chee Lo , Jeffrey Turner
IPC分类号： G06F12/08 , G01R31/28 , G06F11/00 , G06F11/10 , G06F12/16 , G11C29/00
CPC分类号： G06F11/1032 , G06F12/0802
摘要： An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addressed storage compartment of a second memory device are automatically retrieved and provided responsive to the request. As an example, the memory device may be a cache and the second memory device may be main memory for the computing system.
摘要翻译：为计算系统的存储器件提供自主的错误恢复方法。响应于对数据的请求，测试存储器设备的寻址数据和相关控制信息的错误。如果检测到错误，则响应于该请求，自动地检索并提供第二存储设备的寻址存储隔间的内容。作为示例，存储器设备可以是高速缓存，并且第二存储器设备可以是计算系统的主存储器。

3. 发明授权

US07167952B2 Method and system for performing a memory-mode write to cache 失效
标题翻译：执行存储器模式写入高速缓存的方法和系统
公开(公告)号：US07167952B2
公开(公告)日：2007-01-23
申请号：US10667235
申请日：2003-09-17
申请人： Krishna M. Desai , Anil S. Keste , Tin-chee Lo , Thomas D. Needham , Yuk-Ming Ng , Jeffrey M. Turner
发明人： Krishna M. Desai , Anil S. Keste , Tin-chee Lo , Thomas D. Needham , Yuk-Ming Ng , Jeffrey M. Turner
IPC分类号： G06F12/00
CPC分类号： G06F12/0802 , G06F2212/2515 , G06F2212/601
摘要： A method of writing to cache including initiating a write operation to a cache. In a first operational mode, the presence or absence of a write miss is detected and if a write miss is absent, writing data to the cache and if a write miss is present, retrieving the data from a further memory and writing the data to the cache based on least recently used logic. In a second operational mode, the cache is placed in a memory mode and the data is written to the cache based on an address regardless of whether a write miss is present or absent.
摘要翻译：一种写入缓存的方法，包括启动对高速缓存的写操作。在第一操作模式中，检测到存在或不存在写入缺失，并且如果不存在写入缺失，则将数据写入高速缓存并且如果存在写入错误，则从另一存储器检索数据并将数据写入到基于最近最少使用的逻辑缓存。在第二操作模式中，将高速缓存置于存储器模式中，并且基于地址将数据写入高速缓存，而不管存在写缺失是否存在。

4. 发明授权

US5565808A Latch control circuit 失效
标题翻译：锁存控制电路
公开(公告)号：US5565808A
公开(公告)日：1996-10-15
申请号：US461482
申请日：1995-06-05
申请人： Tin-chee Lo
发明人： Tin-chee Lo
IPC分类号： H03K19/003 , H03K3/037 , H03K19/0948 , H03K19/096 , H03K3/356
CPC分类号： H03K3/037
摘要： A latch, connected between an input self-reset dynamic MOS logic circuit and an output self-reset dynamic MOS logic circuit, is provided with clocked interface circuitry to assure proper latching of the state of the input logic in the latch and provides a pulsed output to the output logic circuit. Circuitry is provided to control the self-reset operation of the input logic circuit such that the reset does not occur until a predetermined period of time after the leading edge of the clock pulse latching the state of the input self-reset circuit in the latch. The output of the latch is gated from the latch to the output self-reset circuit under the control of a chopper circuit. The chopper circuit provides a control pulse to gate the state of the latch to the output self-reset circuit a predetermined period of time after the data has been latched. The control pulse has a duration sufficient to assure that the state of the latch is registered in the output self-reset logic.
摘要翻译：连接在输入自复位动态MOS逻辑电路和输出自复位动态MOS逻辑电路之间的锁存器提供有时钟接口电路，以确保锁存器中输入逻辑的状态的适当锁存，并提供脉冲输出到输出逻辑电路。提供电路以控制输入逻辑电路的自复位操作，使得在时钟脉冲的前沿锁存锁存器中的输入自复位电路的状态之后的预定时间段之后，复位不会发生。在斩波电路的控制下，锁存器的输出从锁存器输出到输出自复位电路。斩波电路提供控制脉冲，以在数据被锁存之后的预定时间段内将锁存器的状态门控到输出自复位电路。控制脉冲具有足以确保锁存器的状态被登记在输出自复位逻辑中的持续时间。

5. 发明申请

US20050038974A1 Group write slave and a method for using same 有权
标题翻译：组写从属和使用它的方法
公开(公告)号：US20050038974A1
公开(公告)日：2005-02-17
申请号：US10949629
申请日：2004-09-24
申请人： Tin-chee Lo , Yuk-Ming Ng , Anil Keste
发明人： Tin-chee Lo , Yuk-Ming Ng , Anil Keste
IPC分类号： G06F15/78 , G06F15/00
CPC分类号： G06F15/78
摘要： A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.
摘要翻译：一种使用组写入从机和包括识别级的序列对准逻辑模块的设计和方法，所述识别级具有第一ID输入，第二ID输入，ID与门和ID比较器，选择级，选择级，具有第一选择输入端口，组写入比较器，单独选择比较器，或门和选择与门，从模块，其中从模块包括组等待信号和组后位信号和序列对准逻辑模块，其包括具有逻辑电路的门控逻辑部分，逻辑电路被构造为通过排序和组合多个序列比对逻辑模块输入信号来创建序列比对逻辑模块输出信号，以便表示序列比对逻辑模块输入信号中最慢的。

6. 发明授权

US5488319A Latch interface for self-reset logic 失效
标题翻译：锁定接口用于自复位逻辑
公开(公告)号：US5488319A
公开(公告)日：1996-01-30
申请号：US292673
申请日：1994-08-18
申请人： Tin-chee Lo
发明人： Tin-chee Lo
IPC分类号： H03K19/003 , H03K3/037 , H03K19/0948 , H03K19/096
CPC分类号： H03K3/037
摘要： A latch, connected between an input self-reset dynamic MOS logic circuit and an output self-reset dynamic MOS logic circuit, is provided with clocked interface circuitry to assure proper latching of the state of the input logic in the latch and provides a pulsed output to the output logic circuit. Circuitry is provided to control the self-reset operation of the input logic circuit such that the reset does not occur until a predetermined period of time after the leading edge of the clock pulse latching the state of the input self-reset circuit in the latch. The output of the latch is gated from the latch to the output self-reset circuit under the control of a chopper circuit. The chopper circuit provides a control pulse to gate the state of the latch to the output self-reset circuit a predetermined period of time after the data has been latched. The control pulse has a duration sufficient to assure that the state of the latch is registered in the output self-reset logic.
摘要翻译：连接在输入自复位动态MOS逻辑电路和输出自复位动态MOS逻辑电路之间的锁存器提供有时钟接口电路，以确保锁存器中输入逻辑的状态的适当锁存，并提供脉冲输出到输出逻辑电路。提供电路以控制输入逻辑电路的自复位操作，使得在时钟脉冲的前沿锁存锁存器中的输入自复位电路的状态之后的预定时间段之后，复位不会发生。在斩波电路的控制下，锁存器的输出从锁存器输出到输出自复位电路。斩波电路提供控制脉冲，以在数据被锁存之后的预定时间段内将锁存器的状态门控到输出自复位电路。控制脉冲具有足以确保锁存器的状态被登记在输出自复位逻辑中的持续时间。

7. 发明授权

US06910165B2 Digital random noise generator 失效
标题翻译：数字随机噪声发生器
公开(公告)号：US06910165B2
公开(公告)日：2005-06-21
申请号：US09795899
申请日：2001-02-28
申请人： Howard H. Chen , Li-Kong Wang , Louis L. Hsu , Sang H. Dhong , Tin-chee Lo
发明人： Howard H. Chen , Li-Kong Wang , Louis L. Hsu , Sang H. Dhong , Tin-chee Lo
IPC分类号： G01R31/28 , H03K3/84 , G06F11/00
CPC分类号： H03K3/84 , G01R31/2841
摘要： A system and method for generating random noise for use in testing electronic devices comprises a first random pattern generator circuit for generating first sets of random bit pattern signals; one or more delay devices each receiving a trigger input signal and a random bit pattern signal set for generating in response a respective delay output signal, each delay output signal being delayed in time with respect to a respective trigger signal, a delay time being determined by the bit pattern set received; and, an oscillator circuit device associated with a respective one or more delay devices for receiving a respective delay output signal therefrom and generating a respective oscillating signal, each oscillator signal generated being used to generate artificial random noise for emulating a real noise environment in an electronic device. A second random pattern generator circuit may be provided for generating second sets of random bit pattern signals for receipt by each of the associated oscillator circuit devices in order to frequency adjust in a random manner, each of the oscillator signals.
摘要翻译：用于产生用于测试电子设备的随机噪声的系统和方法包括：第一随机模式发生器电路，用于产生第一组随机位模式信号; 每个接收触发输入信号的一个或多个延迟装置和随机位模式信号组，用于响应于相应的延迟输出信号而产生，每个延迟输出信号相对于相应的触发信号在时间上延迟，延迟时间由接收到位模式集; 以及与相应的一个或多个延迟装置相关联的振荡器电路装置，用于从其接收相应的延迟输出信号并产生相应的振荡信号，所产生的每个振荡器信号用于产生人造随机噪声，以仿真电子中的实际噪声环境设备。可以提供第二随机模式发生器电路，用于产生第二组随机位模式信号，以便由每个相关联的振荡器电路装置接收，以便随机地调整每个振荡器信号。

8. 发明授权

US06836840B2 Slaves with identification and selection stages for group write 失效
标题翻译：具有组写入识别和选择阶段的从站
公开(公告)号：US06836840B2
公开(公告)日：2004-12-28
申请号：US09918189
申请日：2001-07-30
申请人： Tin-chee Lo , Yuk-Ming Ng , Anil S. Keste
发明人： Tin-chee Lo , Yuk-Ming Ng , Anil S. Keste
IPC分类号： G06F1516
CPC分类号： G06F15/78
摘要： A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.
摘要翻译：一种使用组写入从机和包括识别级的序列对准逻辑模块的设计和方法，所述识别级具有第一ID输入，第二ID输入，ID与门和ID比较器，选择级，选择级，具有第一选择输入端口，组写入比较器，单独选择比较器，或门和选择与门，从模块，其中从模块包括组等待信号和组后位信号和序列对准逻辑模块，其包括具有逻辑电路的门控逻辑部分，逻辑电路被构造为通过排序和组合多个序列比对逻辑模块输入信号来创建序列比对逻辑模块输出信号，以便表示序列比对逻辑模块输入信号中最慢的。

9. 发明授权

US06594196B2 Multi-port memory device and system for addressing the multi-port memory device 失效
公开(公告)号：US06594196B2
公开(公告)日：2003-07-15
申请号：US09725967
申请日：2000-11-29
申请人： Louis L Hsu , Tin-chee Lo , Li-Kong Wang
发明人： Louis L Hsu , Tin-chee Lo , Li-Kong Wang
IPC分类号： G11C800
CPC分类号： G06F13/18 , G11C7/1075 , G11C8/16 , G11C11/405
摘要： A multi-port memory array is associated with wordlines and bit-lines to perform data read/write operation and has multi-port memory cells each of which includes multiple ports through which the wordlines and bit-lines are provided, multiple transistor devices each of which corresponds to each of the multiple ports and is coupled to a wordline and a bit-line through a corresponding port, each transistor device being gated by a wordline and having a conduction path of which a first end is connected to a bit-line, and a charge storage device commonly connected to a second end of a conduction path of each of the transistor devices, where the charge storage device is charged when any of the plurality of transistor devices is activated. A system for addressing the multi-port memory array includes a conflict detector for detecting a conflict between two or more of the row address signals to generate a conflict control signal corresponding to the conflict detected, a priority logic circuit for performing a logic operation with respect to the request command signals based on a predetermined priority logic to generate prioritized signals, and a selection unit for selecting one of a request command signal and a prioritized signal corresponding to the request command signal in response to the conflict control signal, where a signal selected by the selection unit selects a corresponding one of the row address signals.

10. 发明授权

US07076676B2 Sequence alignment logic for generating output representing the slowest from group write slaves response inputs 有权
标题翻译：用于从组写入从站响应输入生成表示最慢的输出的序列对齐逻辑
公开(公告)号：US07076676B2
公开(公告)日：2006-07-11
申请号：US10949629
申请日：2004-09-24
申请人： Tin-chee Lo , Yuk-Ming Ng , Anil S. Keste
发明人： Tin-chee Lo , Yuk-Ming Ng , Anil S. Keste
IPC分类号： G06F1/04 , G06F15/16
CPC分类号： G06F15/78
摘要： A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.
摘要翻译：一种使用组写入从机和包括识别级的序列对准逻辑模块的设计和方法，所述识别级具有第一ID输入，第二ID输入，ID与门和ID比较器，选择级，选择级，具有第一选择输入端口，组写入比较器，单独选择比较器，或门和选择与门，从模块，其中从模块包括组等待信号和组后位信号和序列对准逻辑模块，其包括具有逻辑电路的门控逻辑部分，逻辑电路被构造为通过排序和组合多个序列比对逻辑模块输入信号来创建序列比对逻辑模块输出信号，以便表示序列比对逻辑模块输入信号中最慢的。

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