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1. 发明授权

US06836840B2 Slaves with identification and selection stages for group write 失效
标题翻译：具有组写入识别和选择阶段的从站
公开(公告)号：US06836840B2
公开(公告)日：2004-12-28
申请号：US09918189
申请日：2001-07-30
申请人： Tin-chee Lo , Yuk-Ming Ng , Anil S. Keste
发明人： Tin-chee Lo , Yuk-Ming Ng , Anil S. Keste
IPC分类号： G06F1516
CPC分类号： G06F15/78
摘要： A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.
摘要翻译：一种使用组写入从机和包括识别级的序列对准逻辑模块的设计和方法，所述识别级具有第一ID输入，第二ID输入，ID与门和ID比较器，选择级，选择级，具有第一选择输入端口，组写入比较器，单独选择比较器，或门和选择与门，从模块，其中从模块包括组等待信号和组后位信号和序列对准逻辑模块，其包括具有逻辑电路的门控逻辑部分，逻辑电路被构造为通过排序和组合多个序列比对逻辑模块输入信号来创建序列比对逻辑模块输出信号，以便表示序列比对逻辑模块输入信号中最慢的。

2. 发明授权

US07167952B2 Method and system for performing a memory-mode write to cache 失效
标题翻译：执行存储器模式写入高速缓存的方法和系统
公开(公告)号：US07167952B2
公开(公告)日：2007-01-23
申请号：US10667235
申请日：2003-09-17
申请人： Krishna M. Desai , Anil S. Keste , Tin-chee Lo , Thomas D. Needham , Yuk-Ming Ng , Jeffrey M. Turner
发明人： Krishna M. Desai , Anil S. Keste , Tin-chee Lo , Thomas D. Needham , Yuk-Ming Ng , Jeffrey M. Turner
IPC分类号： G06F12/00
CPC分类号： G06F12/0802 , G06F2212/2515 , G06F2212/601
摘要： A method of writing to cache including initiating a write operation to a cache. In a first operational mode, the presence or absence of a write miss is detected and if a write miss is absent, writing data to the cache and if a write miss is present, retrieving the data from a further memory and writing the data to the cache based on least recently used logic. In a second operational mode, the cache is placed in a memory mode and the data is written to the cache based on an address regardless of whether a write miss is present or absent.
摘要翻译：一种写入缓存的方法，包括启动对高速缓存的写操作。在第一操作模式中，检测到存在或不存在写入缺失，并且如果不存在写入缺失，则将数据写入高速缓存并且如果存在写入错误，则从另一存储器检索数据并将数据写入到基于最近最少使用的逻辑缓存。在第二操作模式中，将高速缓存置于存储器模式中，并且基于地址将数据写入高速缓存，而不管存在写缺失是否存在。

3. 发明授权

US07076676B2 Sequence alignment logic for generating output representing the slowest from group write slaves response inputs 有权
标题翻译：用于从组写入从站响应输入生成表示最慢的输出的序列对齐逻辑
公开(公告)号：US07076676B2
公开(公告)日：2006-07-11
申请号：US10949629
申请日：2004-09-24
申请人： Tin-chee Lo , Yuk-Ming Ng , Anil S. Keste
发明人： Tin-chee Lo , Yuk-Ming Ng , Anil S. Keste
IPC分类号： G06F1/04 , G06F15/16
CPC分类号： G06F15/78
摘要： A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.
摘要翻译：一种使用组写入从机和包括识别级的序列对准逻辑模块的设计和方法，所述识别级具有第一ID输入，第二ID输入，ID与门和ID比较器，选择级，选择级，具有第一选择输入端口，组写入比较器，单独选择比较器，或门和选择与门，从模块，其中从模块包括组等待信号和组后位信号和序列对准逻辑模块，其包括具有逻辑电路的门控逻辑部分，逻辑电路被构造为通过排序和组合多个序列比对逻辑模块输入信号来创建序列比对逻辑模块输出信号，以便表示序列比对逻辑模块输入信号中最慢的。

4. 发明申请

US20050060494A1 Method and system for performing a memory-mode write to cache 失效
标题翻译：执行存储器模式写入高速缓存的方法和系统
公开(公告)号：US20050060494A1
公开(公告)日：2005-03-17
申请号：US10667235
申请日：2003-09-17
申请人： Krishna Desai , Anil Keste , Tin-Chee Lo , Thomas Needham , Yuk-Ming Ng , Jeffrey Turner
发明人： Krishna Desai , Anil Keste , Tin-Chee Lo , Thomas Needham , Yuk-Ming Ng , Jeffrey Turner
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0802 , G06F2212/2515 , G06F2212/601
摘要： A method of writing to cache including initiating a write operation to a cache. In a first operational mode, the presence or absence of a write miss is detected and if a write miss is absent, writing data to the cache and if a write miss is present, retrieving the data from a further memory and writing the data to the cache based on least recently used logic. In a second operational mode, the cache is placed in a memory mode and the data is written to the cache based on an address regardless of whether a write miss is present or absent.
摘要翻译：一种写入缓存的方法，包括启动对高速缓存的写操作。在第一操作模式中，检测到存在或不存在写入缺失，并且如果不存在写入缺失，则将数据写入高速缓存并且如果存在写入错误，则从另一存储器检索数据并将数据写入到基于最近最少使用的逻辑缓存。在第二操作模式中，将高速缓存置于存储器模式中，并且基于地址将数据写入高速缓存，而不管存在写缺失是否存在。

5. 发明授权

US07587543B2 Apparatus, method and computer program product for dynamic arbitration control 失效
标题翻译：用于动态仲裁控制的装置，方法和计算机程序产品
公开(公告)号：US07587543B2
公开(公告)日：2009-09-08
申请号：US11338209
申请日：2006-01-23
申请人： Daniele Di Genova , Tin-Chee Lo , Yuk-Ming Ng , Jeffrey M. Turner
发明人： Daniele Di Genova , Tin-Chee Lo , Yuk-Ming Ng , Jeffrey M. Turner
IPC分类号： G06F12/00 , G06F13/14 , G06F13/38 , G06F13/00 , G06F11/00
CPC分类号： G06F13/362 , G06F12/1009 , G06F13/4031
摘要： A dynamic arbitration controller includes components for reading current state information as well as records of known arbitration states which may cause a deadlock condition, comparing the current state to the records of known arbitration states and resolving deadlock conditions during arbitration. The dynamic arbitration controller may include circuits for storing and retrieving information related to the arbitration. The dynamic arbitration controller may be implemented as a circuit design or as a computer program product stored on machine readable media.
摘要翻译：动态仲裁控制器包括用于读取当前状态信息的组件以及可能导致死锁状态的已知仲裁状态的记录，将当前状态与已知仲裁状态的记录进行比较，并在仲裁期间解决死锁条件。动态仲裁控制器可以包括用于存储和检索与仲裁有关的信息的电路。动态仲裁控制器可以被实现为电路设计或作为存储在机器可读介质上的计算机程序产品。

6. 发明申请

US20070174530A1 Apparatus, method and computer program product for dynamic arbitration control 失效
标题翻译：用于动态仲裁控制的装置，方法和计算机程序产品
公开(公告)号：US20070174530A1
公开(公告)日：2007-07-26
申请号：US11338209
申请日：2006-01-23
申请人： Daniele Genova , Tin-Chee Lo , Yuk-Ming Ng , Jeffrey Turner
发明人： Daniele Genova , Tin-Chee Lo , Yuk-Ming Ng , Jeffrey Turner
IPC分类号： G06F13/14 , G06F13/38 , G06F13/00
CPC分类号： G06F13/362 , G06F12/1009 , G06F13/4031
摘要： A dynamic arbitration controller includes components for reading current state information as well as records of known arbitration states which may cause a deadlock condition, comparing the current state to the records of known arbitration states and resolving deadlock conditions during arbitration. The dynamic arbitration controller may include circuits for storing and retrieving information related to the arbitration. The dynamic arbitration controller may be implemented as a circuit design or as a computer program product stored on machine readable media.
摘要翻译：动态仲裁控制器包括用于读取当前状态信息的组件以及可能导致死锁状态的已知仲裁状态的记录，将当前状态与已知仲裁状态的记录进行比较，并在仲裁期间解决死锁条件。动态仲裁控制器可以包括用于存储和检索与仲裁有关的信息的电路。动态仲裁控制器可以被实现为电路设计或作为存储在机器可读介质上的计算机程序产品。

7. 发明申请

US20050038974A1 Group write slave and a method for using same 有权
标题翻译：组写从属和使用它的方法
公开(公告)号：US20050038974A1
公开(公告)日：2005-02-17
申请号：US10949629
申请日：2004-09-24
申请人： Tin-chee Lo , Yuk-Ming Ng , Anil Keste
发明人： Tin-chee Lo , Yuk-Ming Ng , Anil Keste
IPC分类号： G06F15/78 , G06F15/00
CPC分类号： G06F15/78
摘要： A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.
摘要翻译：一种使用组写入从机和包括识别级的序列对准逻辑模块的设计和方法，所述识别级具有第一ID输入，第二ID输入，ID与门和ID比较器，选择级，选择级，具有第一选择输入端口，组写入比较器，单独选择比较器，或门和选择与门，从模块，其中从模块包括组等待信号和组后位信号和序列对准逻辑模块，其包括具有逻辑电路的门控逻辑部分，逻辑电路被构造为通过排序和组合多个序列比对逻辑模块输入信号来创建序列比对逻辑模块输出信号，以便表示序列比对逻辑模块输入信号中最慢的。

8. 发明申请

US20090150732A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR INTEGRATED CIRCUIT RECOVERY TESTING USING SIMULATION CHECKPOINTS 有权
标题翻译：使用模拟检测点进行集成电路恢复测试的方法，系统和计算机程序产品
公开(公告)号：US20090150732A1
公开(公告)日：2009-06-11
申请号：US11951431
申请日：2007-12-06
申请人： Donald Jung , John B. Aylward , Yuk-Ming Ng
发明人： Donald Jung , John B. Aylward , Yuk-Ming Ng
IPC分类号： G01R31/3181 , G06F11/26
CPC分类号： G06F11/263 , G01R31/318357
摘要： A method, system, and computer program product for integrated circuit recovery testing using simulation checkpoints is provided. The method includes executing an error injection test on an integrated circuit that includes a plurality of domains and latches. The error injection test includes injecting an error into one of the domains, clock stopping the domain with the error, performing fencing between the domain with the error and the other domains, and quiescing the other domains. A checkpoint is created of a state of the integrated circuit after the clock stopping, fencing and quiescing have been completed. A mainlines test of the integrated circuit is executed. The mainline test includes applying the checkpoint to the integrated circuit, and performing a recovery reset of the stopped domain. It is determined if the mainline test executed correctly and the results of the determining are output.
摘要翻译：提供了一种使用模拟检查点进行集成电路恢复测试的方法，系统和计算机程序产品。该方法包括在包括多个域和锁存器的集成电路上执行错误注入测试。错误注入测试包括将错误注入到其中一个域中，时钟停止域错误，在错误的域和其他域之间执行防护，并停止其他域。在时钟停止，击剑和静音完成后，创建一个集成电路状态的检查点。执行集成电路的主线测试。主线测试包括将检查点应用于集成电路，并执行停止域的恢复重置。确定是否正确执行主线测试，并输出确定结果。

9. 发明授权

US07721176B2 Method, system, and computer program product for integrated circuit recovery testing using simulation checkpoints 有权
标题翻译：方法，系统和计算机程序产品用于集成电路恢复测试使用模拟检查点
公开(公告)号：US07721176B2
公开(公告)日：2010-05-18
申请号：US11951431
申请日：2007-12-06
申请人： Donald Jung , John B. Aylward , Yuk-Ming Ng
发明人： Donald Jung , John B. Aylward , Yuk-Ming Ng
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/263 , G01R31/318357
摘要： A method, system, and computer program product for integrated circuit recovery testing using simulation checkpoints is provided. The method includes executing an error injection test on an integrated circuit that includes a plurality of domains and latches. The error injection test includes injecting an error into one of the domains, clock stopping the domain with the error, performing fencing between the domain with the error and the other domains, and quiescing the other domains. A checkpoint is created of a state of the integrated circuit after the clock stopping, fencing and quiescing have been completed. A mainlines test of the integrated circuit is executed. The mainline test includes applying the checkpoint to the integrated circuit, and performing a recovery reset of the stopped domain. It is determined if the mainline test executed correctly and the results of the determining are output.
摘要翻译：提供了一种使用模拟检查点进行集成电路恢复测试的方法，系统和计算机程序产品。该方法包括在包括多个域和锁存器的集成电路上执行错误注入测试。错误注入测试包括将错误注入到其中一个域中，时钟停止域错误，在错误的域和其他域之间执行防护，并停止其他域。在时钟停止，击剑和静音完成后，创建一个集成电路状态的检查点。执行集成电路的主线测试。主线测试包括将检查点应用于集成电路，并执行停止域的恢复重置。确定是否正确执行主线测试，并输出确定结果。

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