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1. 发明授权

US5359722A Method for shortening memory fetch time relative to memory store time and controlling recovery in a DRAM 失效
标题翻译：相对于存储器存储时间缩短存储器获取时间并控制DRAM中的恢复的方法
公开(公告)号：US5359722A
公开(公告)日：1994-10-25
申请号：US555960
申请日：1990-07-23
申请人： Shiu K. Chan , Joseph H. Datres, Jr. , Tin-Chee Lo
发明人： Shiu K. Chan , Joseph H. Datres, Jr. , Tin-Chee Lo
IPC分类号： G06F12/06 , G06F12/08 , G11C7/22 , G11C11/401 , G11C11/4076 , G11C29/00 , G11C29/42 , G06F12/00 , G06F1/04
CPC分类号： G11C7/22 , G11C11/4076
摘要： A method for reducing fetch time in a computer system provides a memory fetch cycle that is shorter than the memory store cycle. Each chip of the computer system has at least one dynamic random access memory array (DRAM) and a small high speed cache static random access memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and recovery in the DRAM. The RAS starts DRAM recovery for a fetch cycle at or near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that control DRAM recovery while fetching during DRAM data from the SRAMs, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.
摘要翻译：用于减少计算机系统中的获取时间的方法提供比存储器存储周期短的存储器获取周期。计算机系统的每个芯片在芯片上具有至少一个动态随机存取存储器阵列（DRAM）和小型高速缓存静态随机存取存储器（SRAM）。系统存储器控制器在生成DRAM子地址定时信号（RAS）和高速缓存地址定时信号（CAS）时识别存储器请求的获取或存储状态，用于实现SRAM中的位的访问和寻址以及在SRAM中的恢复 DRAM。在从芯片上的SRAM提取数据开始或接近开始的时候，RAS启动DRAM恢复，但是控制RAS在存储周期之前不开始DRAM恢复，直到完成SRAM数据存储。芯片上的时钟包含控制DRAM恢复的电路，在DRAM的DRAM数据期间提取DRAM，但是防止DRAM恢复开始直到SRAM中的数据存储完成。

2. 发明授权

US4400770A Cache synonym detection and handling means 失效
公开(公告)号：US4400770A
公开(公告)日：1983-08-23
申请号：US205486
申请日：1980-11-10
申请人： Shiu K. Chan , John A. Gerardi , Bruce L. McGilvray
发明人： Shiu K. Chan , John A. Gerardi , Bruce L. McGilvray
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0802
摘要： The disclosure detects and handles synonyms for a store-in-cache (SIC). A processor cache directory (PD) is searched in a principle class addressed by a subset of bits taken from a processor request's logical address. The class address has both translatable and non-translatable bits. If any of the set-associative line entries in the principle class contains the request's translated address, the data is accessed in a corresponding line location in the cache. If the principle class does not have any entry with the request's translated address, a cache miss signal occurs which causes a line fetch command to be generated for main storage to fetch the required line. The line fetch command also causes synonym search circuits to generate the address of every potential synonym class by permutating the translatable bits in the principle class address provided in the line fetch command. Then each potential synonym class is accessed in a copy directory (CD) (which is a copy of essential information in all entries in PD) and compared to the translated request address in order to detect for any existing synonym. Each line entry in the PD and CD also has an exclusive (EX) shareability control bit which controls the handling of a request after detection of a synonym in the CD. If the EX bit is off representing a read only (RO) state, the line cannot be locked during any checkpoint interval. Then the data is not accessed in the detected synonym location, but instead the RO line is copied into an entry in the principle class to improve system performance due to subsequent requests expected to the same line. The synonym line is not invalidated unless the processor is requesting the data exclusively (EX). If the EX bit is on representing an exclusive state in a found synonym entry, the line may be locked in the cache during a checkpoint interval, and therefore the data is accessed in the detected synonym location in the SIC because it cannot then be moved.

3. 发明授权

US4513367A Cache locking controls in a multiprocessor 失效
标题翻译：多处理器中的缓存锁定控件
公开(公告)号：US4513367A
公开(公告)日：1985-04-23
申请号：US246788
申请日：1981-03-23
申请人： Shiu K. Chan , John A. Gerardi , Bruce L. McGilvray
发明人： Shiu K. Chan , John A. Gerardi , Bruce L. McGilvray
IPC分类号： G06F12/08 , G06F12/12 , G06F15/16 , G06F15/177 , G06F13/08
CPC分类号： G06F12/0817 , G06F12/126
摘要： A lock array is provided with bit positions corresponding to each line entry in an associated cache directory. When a lock bit is on, it inhibits the castout, replacement, or invalidation of the associated cache line, which operations are allowed when the lock bit is off. The lock bit may be in an off state while an associated valid bit is set on, but once the lock bit is set on the valid bit cannot be set off until the lock bit is first set off. Lock array controls operate with a replacement selection circuit (which may be conventional) to eliminate each locked line from being a replacement candidate in its congruence class in a set-associative store-in-cache in a multiprocessor (MP). The lock array enables simultaneous reset of all lock bits at each checkpoint without disturbing the status of the associated cache directory. A special type of IE operand request, called a store-interrogate (SI) request, is used to lock the accessed line, whether or not the SI request hits or misses in the cache. Any locked line can continue to receive any fetch, SI, or store cache request from its own IE. Any line remains unlocked as long as it is not accessed by a SI request; that is a line remains unlocked as long as it only receives fetch requests, and fetch requests are generally much more numerous than SI requests. Line locking enables the castout or invalidation of unlocked cache lines during a checkpoint interval.
摘要翻译：锁阵列具有与相关联的高速缓存目录中的每个行条目相对应的位位置。当锁定位打开时，它禁止关联的高速缓存行的转换，替换或无效，当锁定位关闭时允许执行哪些操作。当相关的有效位置1时，锁定位可能处于关闭状态，但一旦锁定位置于有效位之后，才能先锁定锁定位。锁定阵列控制使用替换选择电路（可以是常规的）来消除每个锁定线在多处理器（MP）中的集合关联存储器中的等同类中的替换候选。锁定阵列可以在每个检查点同时复位所有锁定位，而不会干扰相关缓存目录的状态。使用特殊类型的IE操作数请求（称为存储询问（SI）请求）来锁定所访问的行，无论SI请求是否在缓存中命中或丢失。任何锁定的行可以继续从其自己的IE接收任何提取，SI或存储缓存请求。只要SI不被SI请求访问，任何行都将保持解锁; 只要它只接收提取请求，那么一行仍然是解锁的，并且提取请求通常比SI请求多得多。线路锁定可以在检查点间隔期间实现解锁或无效解锁的高速缓存行。

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