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1. 发明授权

US07596734B2 On-Chip AC self-test controller 有权
标题翻译：片上AC自检控制器
公开(公告)号：US07596734B2
公开(公告)日：2009-09-29
申请号：US12185172
申请日：2008-08-04
申请人： John D. Flanagan , Jay R. Herring , Tin-Chee Lo
发明人： John D. Flanagan , Jay R. Herring , Tin-Chee Lo
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G01R31/2891 , G01R31/31922
摘要： A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation is provided. The system includes the system clock, self-test circuitry, a first and second test register to capture and launch test data in response to a sequence of data pulses, and a logic circuit to be tested. The self-test circuitry includes an AC self-test controller and a clock splitter. The clock splitter generates the sequence of data pulses including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse. The at speed data launch pulse and the at speed data capture pulse are generated for a common cycle of the system clock.
摘要翻译：提供了一种用于在包括用于正常操作的系统时钟的集成电路上执行AC自检的系统。该系统包括系统时钟，自检电路，第一和第二测试寄存器，用于响应于数据脉冲序列捕获和发射测试数据，以及待测试的逻辑电路。自检电路包括一个交流自检控制器和时钟分离器。时钟分配器产生数据脉冲序列，包括长数据捕获脉冲，随后是速度数据发射脉冲和速度数据捕获脉冲，随后是长数据发射脉冲。为系统时钟的公共周期产生速度数据发射脉冲和速度数据捕获脉冲。

2. 发明授权

US06738921B2 Clock controller for AC self-test timing analysis of logic system 失效
标题翻译：时钟控制器用于交流自检时序分析逻辑系统
公开(公告)号：US06738921B2
公开(公告)日：2004-05-18
申请号：US09812321
申请日：2001-03-20
申请人： Tinchee Lo , John D. Flanagan
发明人： Tinchee Lo , John D. Flanagan
IPC分类号： G06F104
CPC分类号： G01R31/31858 , G01R31/318577
摘要： A clock controller and clock generating method are provided for AC self-test timing analysis of a logic system. The controller includes latch circuitry which receives a DC input signal at a data input, and a pair of continuous out-of-phase clock signals at capture and launch clock inputs thereof. The latch circuitry outputs two overlapping pulses responsive to the DC input signal going high. The two overlapping pulses are provided to waveform shaper circuitry which produces therefrom two non-overlapping pulses at clock speed of the logic system to be tested. The two non-overlapping pulses are a single pair of clock pulses which facilitate AC self-test timing analysis of the logic system.
摘要翻译：提供时钟控制器和时钟产生方法用于逻辑系统的AC自检时序分析。该控制器包括在数据输入端接收DC输入信号的锁存电路和在其捕捉和发射时钟输入端的一对连续的异相时钟信号。锁存电路输出响应于DC输入信号变高的两个重叠脉冲。两个重叠脉冲被提供给波形整形器电路，其由此产生两个不重叠的脉冲，在待测逻辑系统的时钟速度。两个不重叠的脉冲是一对时钟脉冲，它们有助于逻辑系统的AC自检时序分析。

3. 发明申请

US20080313514A1 ON-CHIP AC SELF-TEST CONTROLLER 有权
标题翻译：片上交流自检器
公开(公告)号：US20080313514A1
公开(公告)日：2008-12-18
申请号：US12185172
申请日：2008-08-04
申请人： John D. Flanagan , Jay R. Herring , Tin-Chee Lo
发明人： John D. Flanagan , Jay R. Herring , Tin-Chee Lo
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31724 , G01R31/2891 , G01R31/31922
摘要： A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation is provided. The system includes the system clock, self-test circuitry, a first and second test register to capture and launch test data in response to a sequence of data pulses, and a logic circuit to be tested. The self-test circuitry includes an AC self-test controller and a clock splitter. The clock splitter generates the sequence of data pulses including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse. The at speed data launch pulse and the at speed data capture pulse are generated for a common cycle of the system clock.
摘要翻译：提供了一种用于在包括用于正常操作的系统时钟的集成电路上执行AC自检的系统。该系统包括系统时钟，自检电路，第一和第二测试寄存器，用于响应于数据脉冲序列捕获和发射测试数据，以及待测试的逻辑电路。自检电路包括一个交流自检控制器和时钟分离器。时钟分配器产生数据脉冲序列，包括长数据捕获脉冲，随后是速度数据发射脉冲和速度数据捕获脉冲，随后是长数据发射脉冲。为系统时钟的公共周期产生速度数据发射脉冲和速度数据捕获脉冲。

4. 发明授权

US07430698B2 Method and system for an on-chip AC self-test controller 有权
标题翻译：一种片上AC自检控制器的方法和系统
公开(公告)号：US07430698B2
公开(公告)日：2008-09-30
申请号：US11323449
申请日：2005-12-30
申请人： John D. Flanagan , Jay R. Herring , Tin-Chee Lo
发明人： John D. Flanagan , Jay R. Herring , Tin-Chee Lo
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G01R31/2891 , G01R31/31922
摘要： A method and system for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation are provided. The method includes applying a long data capture pulse to a first test register in response to the system clock, applying an at speed data launch pulse to the first test register in response to the system clock, inputting the data from the first register to a logic path in response to applying the at speed data launch pulse to the first test register, applying an at speed data capture pulse to a second test register in response to the system clock, inputting the logic path output to the second test register in response to applying the at speed data capture pulse to the second test register, and applying a long data launch pulse to the second test register in response to the system clock.
摘要翻译：提供一种用于在包括在正常操作期间使用的系统时钟的集成电路上执行AC自检的方法和系统。该方法包括响应于系统时钟将长数据捕获脉冲施加到第一测试寄存器，响应于系统时钟向第一测试寄存器应用速度数据发射脉冲，将数据从第一寄存器输入到逻辑响应于将速度数据发射脉冲施加到第一测试寄存器，响应于系统时钟将速度数据捕获脉冲施加到第二测试寄存器，响应于应用将逻辑路径输出输入到第二测试寄存器到第二测试寄存器的速度数据捕获脉冲，以及响应于系统时钟将长数据启动脉冲施加到第二测试寄存器。

5. 发明授权

US4686212A Stable sodium aspirin tablet compositions 失效
标题翻译：稳定的阿斯匹林钠片剂组合物
公开(公告)号：US4686212A
公开(公告)日：1987-08-11
申请号：US765086
申请日：1985-08-13
申请人： Fred P. Ducatman , John D. Flanagan
发明人： Fred P. Ducatman , John D. Flanagan
IPC分类号： A61K9/20 , A61K31/60 , A61K47/02 , A61K47/26 , A61K47/32 , A61K47/44 , A61K31/62
CPC分类号： A61K31/60 , A61K9/2009 , A61K9/2013 , A61K9/2018
摘要： Compositions are provided for the preparation of stable sodium aspirin tablets. The compositions comprise dry, crystalline sodium aspirin, an anhydrous binder that is unreactive to sodium aspirin and a hydrogenated animal or vegetable oil lubricant but lack the traditional tablet disintegrant. Tablets produced from these compositions can be stored for prolonged periods of time yet disintegrate in water at a rate comparable to that of ordinary aspirin.
摘要翻译：提供组合物用于制备稳定的阿司匹林钠片剂。组合物包含干燥，结晶的阿斯匹林钠，对阿斯匹林钠不反应的无水粘合剂和氢化的动物或植物油润滑剂，但不含传统的片剂崩解剂。由这些组合物生产的片剂可以长时间储存，但以与普通阿司匹林相当的速率在水中分解。

6. 发明授权

US07058866B2 Method and system for an on-chip AC self-test controller 失效
标题翻译：一种片上AC自检控制器的方法和系统
公开(公告)号：US07058866B2
公开(公告)日：2006-06-06
申请号：US10131554
申请日：2002-04-24
申请人： John D. Flanagan , Jay R. Herring , Tin-Chee Lo
发明人： John D. Flanagan , Jay R. Herring , Tin-Chee Lo
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G01R31/2891 , G01R31/31922
摘要： A method for performing AC self-test on an integrated circuit, including a system clock for use during normal operation. The method includes applying a long data capture pulse to a first test register in response to the system clock, and further applying at an speed data launch pulse to the first test register in response to the system clock. Inputting the data from the first register to a logic path in response to applying the at speed data launch pulse to the first test register. Applying at speed data capture pulse to a second test register in response to the system clock. Inputting the output from the logic path to the second test register in response to applying the at speed data capture pulse to the second register. Applying a long data launch pulse to the second test register in response to the system clock.
摘要翻译：一种用于在集成电路上执行AC自检的方法，包括在正常操作期间使用的系统时钟。该方法包括响应于系统时钟将长数据捕获脉冲施加到第一测试寄存器，并且响应于系统时钟进一步将速度数据发射脉冲施加到第一测试寄存器。响应于将速度数据发射脉冲应用于第一测试寄存器，将数据从第一寄存器输入到逻辑路径。响应于系统时钟，将速度数据采集脉冲应用到第二个测试寄存器。响应于将速度数据捕获脉冲施加到第二寄存器，将逻辑路径的输出输入到第二测试寄存器。将响应系统时钟的长数据发射脉冲应用于第二个测试寄存器。

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