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1. 发明申请

WO2021183915A1 APPARATUSES AND METHODS INVOLVING AMPLIFICATION CIRCUIT WITH PUSH-PULL WAVE-SHAPING OPERATION 审中-公开
公开(公告)号：WO2021183915A1
公开(公告)日：2021-09-16
申请号：PCT/US2021/022151
申请日：2021-03-12
申请人： THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY
发明人： RIVAS-DAVILA, Juan , GU, Lei , CHEN, Tuofei
IPC分类号： H03K5/00 , H03K7/08 , H03K5/01 , H03K4/02 , H03K5/12
摘要： In certain examples, methods and semiconductor structures are directed to circuit-based apparatus in which an amplifier includes stacked, first and second circuit amplification stages to operate out of phase from one another for providing a push-pull operation, with each of the first and second circuit stages including a switching circuit and an impedance path to drive the switching circuit. The apparatus further includes a waveform-shaping circuit to shape, in response to each of the first and second circuit stages, a voltage signal for presentation to the switching circuit. As may be implemented in various more-specific examples, the apparatus may generate a constant output voltage with high efficiency across a wide range of resistive loads.

2. 发明申请

WO2020049039A1 CIRCUIT ASSEMBLY AND METHOD FOR OPERATING AN LED MODULE 审中-公开
公开(公告)号：WO2020049039A1
公开(公告)日：2020-03-12
申请号：PCT/EP2019/073569
申请日：2019-09-04
申请人： OSRAM GMBH , OSRAM S.P.A. SOCIETA RIUNITE OSRAM EDISON CLERICI
发明人： MÜHLSCHLEGEL, Joachim , GRIFFONI, Alessio , ANGELIN, Francesco , STOCCO, Antonio
IPC分类号： H05B33/08 , H05B45/37 , H03K4/02 , H03K5/01
摘要： A circuit assembly (100') and a method for operating an LED module (10, 10') is provided, the LED module comprising a plurality of module units (14) which are each interconnected between common connection lines (16, 17) in a sequential order with increasing distances towards a connection terminal (11) of the LED module. The circuit assembly comprises an output terminal (34) comprising a first output terminal portion (34a) and a second output terminal portion (34b), a main power supply (V main) for supplying an operation voltage potential to a first output terminal portion (34a), a control device (50') for generating a pulse width modulation signal, and an electronic switch (40) coupled to the control device (50') and configured to obtain the pulse width modulation signal and arranged to connect and disconnect a second output terminal portion (34b) to/from a reference potential in accordance with the pulse width modulation signal, such as to supply a pulse width modulated voltage to the output terminal (34). A pulse shaping unit (70) is coupled to the control device (50') and configured to store electrical energy, when the electronic switch disconnects the second output terminal portion (34b) from the reference potential, and to release the stored electrical energy to the output terminal (34), when the electronic switch (40) connects the second output terminal portion (34b) with the reference potential.

3. 发明申请

WO2012011824A1 IMPROVEMENTS RELATING TO HIGH SPEED PULSE SHAPING TECHNOLOGY 审中-公开
标题翻译：关于高速脉冲成形技术的改进
公开(公告)号：WO2012011824A1
公开(公告)日：2012-01-26
申请号：PCT/NZ2011/000141
申请日：2011-07-21
申请人： FREI, Dr. Matthias
发明人： FREI, Dr. Matthias
IPC分类号： H03K5/01
CPC分类号： H03K3/02 , G01S7/282 , G06F1/02 , G11B20/10037 , G11B2220/2516 , H03C1/00
摘要： A circuit adapted to generate a high speed shaped pulse comprising an input adapted to receive a data signal and a control signal. A plurality of logic elements are configures to receive the data signal and the control signal and generate a plurality of output signals representative of the shaped pulse. A digital to analog converter is adapted to receive the plurality of output signals and generate a shaped pulse.
摘要翻译：一种适于产生高速成形脉冲的电路，包括适于接收数据信号和控制信号的输入。多个逻辑元件是用于接收数据信号和控制信号并生成表示成形脉冲的多个输出信号的配置。数模转换器适于接收多个输出信号并产生成形脉冲。

4. 发明申请

WO2007059392A2 ACTIVE SIGNAL MANAGEMENT IN CABLES AND OTHER INTERCONNECTS 审中-公开
标题翻译：电缆和其他互连中的主动信号管理
公开(公告)号：WO2007059392A2
公开(公告)日：2007-05-24
申请号：PCT/US2006/060611
申请日：2006-11-07
申请人： VIZIONWARE, INC.
发明人： EGAN, Kenneth W. , CHANDLER, Gregory T. , BREHMER, Geoffrey E. , SHEAFOR, Stephen J.
IPC分类号： H03K5/01
CPC分类号： H03K19/00346 , G06F3/14 , G09G5/006 , G09G5/008 , G09G2330/06 , G09G2370/04 , G09G2370/10 , G09G2370/12 , H03K5/135 , H03K19/00361 , H03K19/0175 , H03M9/00 , H04L25/14
摘要： Transmit-side active signal management circuitry applies active signal management processes to a digital signal at a transmit side of an interconnect. At the receive side of the interconnect, receive-side active signal management circuitry applies one or more corresponding active signal management processes, as appropriate, to the received digital signal to recover the information represented by the original digital signal. The interconnect can include a cable used to transmit the signals between a source device and a destination device, whereby one or both of the transmit-side active signal management circuitry and the receive-side active signal management circuitry is implemented at a corresponding cable receptacle of the cable. Alternately, one or both of the transmit-side active signal management circuitry and the receive-side active signal management circuitry can be implemented at a cable adaptor, thereby permitting the use of a passive cable interconnect to transmit the signal.
摘要翻译：发射侧有源信号管理电路将有源信号管理过程应用到互连发射侧的数字信号。在互连的接收侧，接收侧有源信号管理电路根据接收的数字信号适当地应用一个或多个相应的有源信号管理处理，以恢复由原始数字信号表示的信息。互连可以包括用于在源设备和目的地设备之间传输信号的电缆，由此发射侧有源信号管理电路和接收侧有源信号管理电路中的一个或两个在相应的电缆接口电缆。或者，可以在电缆适配器处实现发射侧有源信号管理电路和接收侧有源信号管理电路中的一个或两个，从而允许使用无源电缆互连来发送信号。

5. 发明申请

WO2007028236A2 SYSTEM AND METHOD FOR DELIVERY OF VIDEO, CONTENT ON DEMAND AND IP PACKETS 审中-公开
标题翻译：用于传送视频，内容和IP分组的系统和方法
公开(公告)号：WO2007028236A2
公开(公告)日：2007-03-15
申请号：PCT/CA2006/001455
申请日：2006-09-05
申请人： LIQUID XSTREAM SYSTEMS INC. , DUFRESNE, Benoît , KISOVEC
发明人： DUFRESNE, Benoît , KISOVEC
IPC分类号： H03K5/01 , H03K5/08 , H03K7/00 , H04L27/00 , H04N7/173 , H04N7/24
CPC分类号： H04L25/03834 , H04L27/362 , H04N7/17318 , H04N21/2383 , H04N21/47202
摘要： The present application describes a method and filter for shaping a series of pulses spaced in time for subsequent transmission in a communications system, each of the pulses having a magnitude comprising the steps of providing a generic shaped pulse, for each pulse in the series, generating a shaped pulse by scaling the generic shaped pulse by an amount proportional to the magnitude, wherein at least a portion of each generated pulse overlaps in time with at least a portion of at least one subsequent generated pulse, and combining the overlapping portions of the generated pulses. The present application also describes a method and apparatus for modulating an input signal comprised of an ordered series of samples separated by a substantially constant period T comprising the steps of providing a carrier signal, the carrier signal comprised of a series of samples separated by a substantially constant period T, wherein one of the carrier samples corresponds to each of the input signal samples, selecting a plurality of N successive samples from the series of input signal samples, the series of samples having an input order, for each of the N selected samples in parallel, multiplying the selected sample by the corresponding carrier sample and recombining the N multiplied samples while maintaining the input order.
摘要翻译：本申请描述了一种用于对一系列脉冲进行整形以在随后的通信系统中传输的脉冲的方法和滤波器，每个脉冲具有幅度，包括为串联中的每个脉冲提供通用成形脉冲的步骤，通过将通用成形脉冲缩放与幅度成比例的量的成形脉冲，其中每个产生的脉冲的至少一部分在时间上与至少一个后续产生的脉冲的至少一部分重叠，并且将所产生的脉冲的重叠部分脉冲。本申请还描述了一种用于调制包括由基本上恒定的周期T分离的有序序列的输入信号的方法和装置，包括以下步骤：提供载波信号，载波信号由一系列采样分离的样本恒定周期T，其中载波样本中的一个对应于每个输入信号样本，从所述一系列输入信号样本中选择多个N个连续样本，对于所选N个样本中的每一个，所述一系列样本具有输入阶数并行地，将所选择的样本乘以相应的载波样本，并重新组合N个相乘的样本，同时保持输入顺序。

6. 发明申请

WO2006119751A2 VERFAHREN UND EINRICHTUNG ZUR ELEKTRISCHEN ANSTEUERUNG EINES VENTILS MIT EINEM MECHANISCHEN SCHLIEßELEMENT 审中-公开
标题翻译：方法和设备的控制电动阀用机械密封元件
公开(公告)号：WO2006119751A2
公开(公告)日：2006-11-16
申请号：PCT/DE2006/000814
申请日：2006-05-12
申请人： CONTI TEMIC MICROELECTRONIC GMBH , LEIPNITZ, Klaus
发明人： LEIPNITZ, Klaus
IPC分类号： F02D41/02 , F16H61/02 , F16K29/00 , B60G17/018 , H03K5/01
CPC分类号： F16K31/0675 , F02D41/004 , F02D41/1408 , F15B2211/328 , F15B2211/427 , F15B2211/527 , H03K7/08
摘要： Das Verfahren und die Einrichtung dienen zur elektrischen Ansteuerung eines Ventils (2) mit einem mechanischen Schließelement (4) mittels eines elektrischen Stromes (I). Letzterer wird mittels eines pulsweitenmodulierten PWM-Signals (S p ) erzeugt wird, das eine PWM-Periodendauer (T PWM ) und ein Tastverhältnis aufweist. Ein Tastverhältnissignal (TV) setzt sich aus einem Grundanteil (S Q ) und einem Überlagerungsanteil (S Ü ) mit einer Überlagerungsperiodendauer (T Ü ) zusammen, innerhalb der das Tastverhältnissignal (TV) zwischen einem hohen und einem niedrigen Tastverhältniswert umgeschaltet wird. Es wird überprüft, ob die Addition des Grundanteils (S G ) und des ursprünglichen Überlagerungsanteils (S Ü ) einen fiktiven Tastverhältniswert von kleiner als Null oder von größer als Eins liefert. Falls ja wird eine Korrektur vorgenommen, indem der niedrige Tastverhältnis wert auf mindestens Null und der hohe Tastverhältnis wert angehoben wird bzw. der hohe Tastverhältniswert auf höchstens Eins und der niedrige Tastverhältniswert abgesenkt wird, und indem eine Tastverhältnisdauer vom Beginn der Überlagerungsperiodendauer (T Ü ) bis zum Umschalten zwischen den beiden Tastverhältniswerten als ein ganzzahliges Vielfaches der PWM-Periodendauer (T PWM ) eingestellt wird. Bei der Korrektur wird der Mittelwert des Tastverhältnissignals (TV) nicht verändert.
摘要翻译：该方法和设备被用于通过电流（I）的装置的阀（2）与机械锁定元件（4）的电控制。后者（S _{P ）由具有一个PWM周期持续时间的脉冲宽度调制PWM信号（T _{PWM ）和占空比生成。占空比信号（TV）是由一基底部分的（S _{Q ），并与覆盖周期（T _{OB ）的覆盖部（S _{OB ）一起高和低占空比值之间，其占空比（TV）内进行切换。检查是否加入碱部分的（S ）和原始覆盖部（S _{Ü）返回小于零或大于一的假想的占空比。如果是的话，校正由低占空比制成值得增加值至少为零，高占空比或高占空比降低到最多一个的和低占空比和由Tastverhältnisdauer（从重叠期间T _{的开始 Ü）到两个占空比值之间的切换（作为时间t _{PWM ）PWM周期的整数倍被设置。在校正占空比信号（TV）的平均值不变化。}}}}}}}}

7. 发明申请

WO2005034371A3 ADAPTIVE PER-PAIR SKEW COMPENSATION METHOD FOR EXTENDED REACH DIFFERENTIAL TRANSMISSION 审中-公开
标题翻译：针对扩展到达差分传输的自适应全双工补偿方法
公开(公告)号：WO2005034371A3
公开(公告)日：2005-06-23
申请号：PCT/US2004032089
申请日：2004-09-27
申请人： KEYEYE
发明人： DYER KENNETH C , TAKATORI HIROSHI
IPC分类号： H03K5/01 , H03K5/135 , H04B20060101 , H04L7/00 , H04L25/02 , H04L25/08
CPC分类号： H03K5/135 , H04L25/0272 , H04L25/0292 , H04L25/08
摘要： High speed data transmission schemes often use differential lines to reduce the effect of noise on the data signal. Unfortunately, the signal propagation on the positive and negative lines may be different, which leads to a signal skew problem. This document describes a novel way of compensating for differential line skew in data transmission lines.
摘要翻译：高速数据传输方案通常使用差分线路来减少噪声对数据信号的影响。不幸的是，正负线上的信号传播可能不同，这导致信号偏斜问题。本文介绍了一种补偿数据传输线路中的差分线偏移的新方法。

8. 发明申请

WO2004073293A2 40-GB/S CLOCK AND DATA RECOVERY CIRCUIT IN 0.18 MICROMETERS TECHNOLOGY 审中-公开
标题翻译： 0.18微米技术中的40 GB / S时钟和数据恢复电路
公开(公告)号：WO2004073293A2
公开(公告)日：2004-08-26
申请号：PCT/US2004001208
申请日：2004-01-16
申请人： UNIV CALIFORNIA , LEE JRI , RAZAVI BEHZAD
发明人： LEE JRI , RAZAVI BEHZAD
IPC分类号： H03K3/3562 , H03K3/86 , H03K5/00 , H03K5/01 , H03K5/14 , H03K19/21 , H03L7/091 , H03L7/099 , H04L7/033 , H04N20060101 , H04N
CPC分类号： H03L7/0995 , H03K3/3562 , H03K3/86 , H03K5/14 , H03K19/215 , H03K2005/00032 , H03L7/091 , H04L7/033
摘要： A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and demultiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals. The circuit is fabricated in 0.18 µm CMOS technology.
摘要翻译： 40 Gb / s时钟和数据恢复（CDR）电路采用四分之一速率相位检测器和多相压控振荡器，将40 Gb / s输入数据信号重新定时和解复用为四个10 Gb / s输出数据信号。该电路采用0.18微米CMOS技术制造。

9. 发明申请

WO0205262A3 SUB-BAND EXPONENTIAL SMOOTHING NOISE CANCELING SYSTEM 审中-公开
标题翻译：子带指数平滑噪声消除系统
公开(公告)号：WO0205262A3
公开(公告)日：2002-06-13
申请号：PCT/US0119450
申请日：2001-06-19
申请人： ANDREA ELECTRONICS CORP
发明人： BERDUGO BARUCH
IPC分类号： G10L15/20 , G10L11/00 , G10L19/02 , G10L21/02 , H03D1/04 , H03D1/06 , H03K5/01 , H03K6/04 , H04B1/10 , H04L1/00 , H04L25/08
CPC分类号： G10L19/0208 , G10L21/0208 , G10L2021/02168
摘要： A noise canceling method and apparatus for canceling noise by time domain processing sub-bands of a digital input signal. The input signal (102) is divided into a number of frequency-limited time-domain sub-bands (104). Each sub-band is then individually processed in a band splitter (106) to cancel noise present in the signal. The noise processing includes exponential averaging of the input, noise estimation, and subtraction processing. The noise subtraction process is simplified by generating a filter coefficient that is exponentially smoothed, hard limited, and multiplied with the input signal to generate the noise processed output for each sub-band. The noise processed bands are then recombined in a recombiner (108) into a digital output signal (110). Implementation may be effected in software or hardware and applied to various noise canceling and signal processing application.
摘要翻译：一种用于通过数字输入信号的时域处理子带来消除噪声的噪声消除方法和装置。输入信号（102）被分成多个频率受限的时域子频带（104）。然后在分束器（106）中单独处理每个子带以消除信号中存在的噪声。噪声处理包括输入，噪声估计和减法处理的指数平均。通过产生指数平滑，硬限制的滤波器系数并与输入信号相乘以产生每个子带的噪声处理输出来简化噪声减除处理。然后将噪声处理的频带在重组器（108）中重新组合成数字输出信号（110）。实现可以在软件或硬件中实现，并且应用于各种噪声消除和信号处理应用。

10. 发明申请

WO01099279A1 SIGNAL PEAK REDUCTION CIRCUIT FOR NON-CONSTANT ENVELOPE MODULATION SIGNALS 审中-公开
标题翻译：用于非常规信号调制信号的信号峰值减小电路
公开(公告)号：WO01099279A1
公开(公告)日：2001-12-27
申请号：PCT/AU2001/000741
申请日：2001-06-20
IPC分类号： H03H17/02 , H04B1/707 , H04J11/00 , H04L27/26 , H03K5/01
CPC分类号： H04L27/2624 , H03H17/0294 , H04B2201/70706
摘要： A signal peak reduction circuit (10), comprising: a band-limiting filter (13) for limiting the bandwidth of a data bearing signal, a predictive filter (12) for predicting peaks in the data bearing signal at the output of the pulse-shaping filter, a clipping processor (15) for generating a compensation signal in response to one or more signal peaks predicted by the predictive filter, and a signal combining device (16) for applying the compensation signal to the data bearing signal prior to amplification of the data bearing signal.
摘要翻译：一种信号峰值降低电路（10），包括：用于限制数据承载信号的带宽的带限滤波器（13），用于预测所述脉冲宽带信号的输出端的数据承载信号中的峰值的预测滤波器（12）整形滤波器，用于响应于由预测滤波器预测的一个或多个信号峰值产生补偿信号的削波处理器（15），以及用于在放大前将补偿信号施加到数据承载信号的信号组合装置（16）数据承载信号。

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