专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2013055831A1 METHODS AND APPARATUS PROVIDING HIGH-SPEED CONTENT ADDRESSABLE MEMORY (CAM) SEARCH-INVALIDATES 审中-公开
标题翻译：提供高速内容可寻址存储器（CAM）的方法和设备搜索 - 无效
公开(公告)号：WO2013055831A1
公开(公告)日：2013-04-18
申请号：PCT/US2012/059613
申请日：2012-10-10
申请人： QUALCOMM INCORPORATED
发明人： VARMA, Manju Rathna , HOFF, David Paul , MARTZLOFF, Jason Philip
IPC分类号： G11C15/04
CPC分类号： G06F12/00 , G11C15/04
摘要： Embodiments of a Content Addressable Memory (CAM) enabling high-speed search and invalidate operations and methods of operation thereof are disclosed. In one embodiment, the CAM includes a CAM cell array including a number of CAM cells and a valid bit cell (44) configured to generate a match indicator (MATCH LINE), and blocking circuitry (46) configured to block an output of the valid bit cell (44) from altering the match indicator (MATCH LINE) during an invalidate process of a search and invalidate operation. Preferably, the output of the valid bit cell (44) is blocked from affecting the match indicator (MATCH LINE) for the CAM cell array beginning at a start of the invalidate process and continuing until an end of the search and invalidate operation.
摘要翻译：公开了能够进行高速搜索和无效操作的内容可寻址存储器（CAM）的实施例及其操作方法。在一个实施例中，CAM包括包括多个CAM单元的CAM单元阵列和被配置为生成匹配指示符（MATCH LINE）的有效位单元（44），以及阻塞电路（46），其被配置为阻止有效的比特单元（44）在搜索和无效操作的无效处理期间改变匹配指示符（MATCH LINE）。优选地，阻止有效位单元（44）的输出影响从无效过程开始开始的CAM单元阵列的匹配指示符（MATCH LINE），并且继续直到搜索结束和无效操作。

2. 发明申请

WO2014070702A1 DUMMY READ TO PREVENT CROWBAR CURRENT DURING READ-WRITE COLLISIONS IN MEMORY ARRAYS WITH CROSSCOUPLED BITLINE KEEPERS 审中-公开
标题翻译：在使用CROSSCOUPLED BITLINE KEEPERS的存储器阵列中阅读写入冲突之前，请务必阅读并防止曲线电流
公开(公告)号：WO2014070702A1
公开(公告)日：2014-05-08
申请号：PCT/US2013/067193
申请日：2013-10-29
申请人： QUALCOMM INCORPORATED
发明人： SHANKAR, Harish , HOFF, David Paul , GARG, Manish
IPC分类号： G11C8/16 , G11C11/419 , G11C8/08 , G11C11/418
CPC分类号： G11C11/412 , G11C5/063 , G11C8/08 , G11C8/16 , G11C11/413 , G11C11/418
摘要： Systems and methods for detecting and suppressing crowbar currents in memory arrays (200). A dummy read is implemented to prevent crowbar currents in the case of simultaneous read-write collisions in a static random access memory (SRAM) array having cross-coupled bitline keepers (208a-b). When a simultaneous read and write operation to a first entry (202i) of the memory array is detected, the read operation (206i) to the first entry is suppressed and a dummy read operation (206j) to a second entry (202j) of the memory array is performed. The write operation (204i) to the first entry is allowed to proceed undisturbed.
摘要翻译：用于检测和抑制存储器阵列中的撬棒电流的系统和方法（200）。在具有交叉耦合位线保持器（208a-b）的静态随机存取存储器（SRAM）阵列中，在同时读写冲突的情况下，实现虚拟读取以防止撬棒电流。当检测到对存储器阵列的第一条目（202i）的同时读取和写入操作时，对第一条目的读取操作（206i）被抑制，并且虚拟读取操作（206j）到第二条目执行存储器阵列。允许对第一条目的写入操作（204i）不受干扰地进行。

3. 发明申请

WO2013049763A1 METHOD AND APPARATUS OF REDUCING LEAKAGE POWER IN MULTIPLE PORT SRAM MEMORY CELL 审中-公开
标题翻译：减少多端口SRAM存储单元泄漏功率的方法和装置
公开(公告)号：WO2013049763A1
公开(公告)日：2013-04-04
申请号：PCT/US2012/058178
申请日：2012-09-30
申请人： QUALCOMM INCORPORATED , PHAN, Michael ThaiThanh , GARG, Manish , HOFF, David Paul
发明人： PHAN, Michael ThaiThanh , GARG, Manish , HOFF, David Paul
IPC分类号： G11C11/413
CPC分类号： G11C11/413 , G11C5/148
摘要： Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states of the group of memory cells, such that leakage parts are effectively eliminated. The memory array further includes logic for dynamically enabling a selected group of the memory cells during read or write access operations on the selected memory cells, wherein corresponding read or write bitlines are precharged before and after the respective rear or write operations.
摘要翻译：包括诸如8T SRAM单元的存储单元的存储器阵列中的减小泄漏电流和功耗的系统和方法。存储器阵列包括用于在睡眠模式或存储器单元组的非活动状态期间以降低功率状态动态地将一组存储器单元置于存储器阵列中的逻辑，从而有效地消除泄漏部分。存储器阵列还包括用于在对所选择的存储器单元进行读取或写入访问操作期间动态地启用所选存储器单元组的逻辑，其中相应的读取或写入位线在相应的后部或写入操作之前和之后被预充电。

4. 发明申请

WO2014124176A1 HYBRID DYNAMIC-STATIC ENCODER WITH HIT AND MULTI-HIT DETECTION 审中-公开
标题翻译：混合动态静态编码器，具有HIT和多重检测功能
公开(公告)号：WO2014124176A1
公开(公告)日：2014-08-14
申请号：PCT/US2014/015161
申请日：2014-02-06
申请人： QUALCOMM INCORPORATED
发明人： HOFF, David Paul , DELLA ROVA, Tracey A. , MARTZLOFF, Jason P.
IPC分类号： G06F7/74 , G11C15/04 , H03K19/00
CPC分类号： G11C15/04 , G06F7/74 , G11C15/043 , H03K19/0013
摘要： The hybrid dynamic-static encoder described herein combines dynamic and static logic to provide area, power, and leakage savings relative to a fully dynamic encoder with an equivalent logic delay. For example, the hybrid dynamic-static encoder includes identical top and bottom halves, which are combined to produce final encoded index, hit, and multi-hit outputs. Each encoder half uses a dynamic net for each index bit with rows that match a search key dotted. If a row has been dotted to indicate that the row matches the search key, the dynamic nets associated therewith are evaluated to reflect the index associated with the row. Accordingly, the hybrid dynamic-static encoder has a reduced set of smaller dynamic nets that leverage redundant pull-down structures across the index, hit, and multi-hit dynamic nets.
摘要翻译：这里描述的混合动态静态编码器结合动态和静态逻辑以相对于具有等效逻辑延迟的全动态编码器来提供面积，功率和泄漏节约。例如，混合动态静态编码器包括相同的上半部分和下半部分，其被组合以产生最终编码索引，命中和多命中输出。每个编码器一半使用每个索引位的动态网络，其中匹配搜索关键点的行。如果已经点划线以指示该行与搜索关键字相匹配，则评估与之相关联的动态网络以反映与该行相关联的索引。因此，混合动态静态编码器具有减少的较小动态网络的集合，其利用索引，命中和多命中动态网络的冗余下拉结构。

5. 发明申请

WO2013040066A1 ADAPTIVE READ WORDLINE VOLTAGE BOOSTING APPARATUS AND METHOD FOR MULTI-PORT SRAM 审中-公开
标题翻译：适用于多端口SRAM的WORDLINE电压升压装置和方法
公开(公告)号：WO2013040066A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/054907
申请日：2012-09-12
申请人： QUALCOMM INCORPORATED , GARG, Manish , PHAN, Michael ThaiThanh , HOFF, David Paul , NGUYEN, Quan
发明人： GARG, Manish , PHAN, Michael ThaiThanh , HOFF, David Paul , NGUYEN, Quan
IPC分类号： G11C11/419 , G11C8/08 , G11C11/418
CPC分类号： G11C11/419 , G11C8/08 , G11C11/418
摘要： Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) (104) in response to process-voltage-temperature variations when needed. Embodiments include a critical path (114) that simulates a typical memory cell (104) and read-out circuit (102) in the SRAM. Applying a trigger signal to a word-line input port (123) of the critical path, and comparing the output (125) of the critical path to a reference-latch signal (127), provides an indication of when to boost the supply voltage to the read-out circuits of the SRAM.
摘要翻译：本发明的实施例涉及用于在需要时响应于过程电压 - 温度变化自适应地将SRAM的电源电压升高到SRAM（静态随机存取存储器）（104）的系统和方法。实施例包括模拟SRAM中的典型存储单元（104）和读出电路（102）的关键路径（114）。将触发信号施加到关键路径的字线输入端口（123），并将关键路径的输出（125）与参考锁存信号（127）进行比较，提供何时升压电源电压的指示到SRAM的读出电路。

6. 发明申请

WO2017200657A1 EFFICIENT COMPARE OPERATION 审中-公开
标题翻译：有效的比较操作
公开(公告)号：WO2017200657A1
公开(公告)日：2017-11-23
申请号：PCT/US2017/026605
申请日：2017-04-07
申请人： QUALCOMM INCORPORATED
发明人： HOFF, David Paul , LILES, Stephen Edward , REED, Brian Joy
IPC分类号： G06F12/0895 , G11C15/04 , G11C7/10
摘要： Systems and methods relate to memory operations in a memory array. A compare operation is performed using a sense amplifier. True and complement versions of a search bit are compared with true and complement versions of a data bit stored in a data row of the memory array to generate true and complement sense amplifier inputs. The true and complement sense amplifier inputs are amplified in the sense amplifier to generate a single-ended match signal. The single-ended match signal can be aggregated with other single-ended match signals in the data row to determine whether there is a hit or miss for a compare operation on the entire data row.
摘要翻译：系统和方法涉及存储器阵列中的存储器操作。使用读出放大器执行比较操作。将搜索位的真和补码版本与存储在存储器阵列的数据行中的数据位的真和补数版本进行比较，以生成真和补充读出放大器输入。真实和互补读出放大器输入在读出放大器中放大以生成单端匹配信号。单端匹配信号可以与数据行中的其他单端匹配信号聚合，以确定整个数据行上的比较操作是否存在命中或未命中。

7. 发明申请

WO2016175958A2 FULLY VALID-GATED READ AND WRITE FOR LOW POWER ARRAY 审中-公开
标题翻译：全功能读取和写入低功耗阵列
公开(公告)号：WO2016175958A2
公开(公告)日：2016-11-03
申请号：PCT/US2016/024478
申请日：2016-03-28
申请人： QUALCOMM INCORPORATED
发明人： HOFF, David Paul , MARTZLOFF, Jason Philip , SWEITZER, Robert Andrew
IPC分类号： G11C7/12 , G11C8/08 , G11C11/419 , G11C7/10
CPC分类号： G11C7/106 , G11C7/10 , G11C7/1009 , G11C7/1066 , G11C7/1087 , G11C7/109 , G11C7/1093 , G11C7/12 , G11C7/22 , G11C8/08 , G11C11/419
摘要： In an array that qualifies each row according to a valid/invalid state, each row may each include valid-gated read circuitry to conditionally block a read wordline from toggling unless the row stores a data word that has a valid state or a read force signal is asserted. Furthermore, in a write operation, each row may have valid-gated write circuitry that conditionally blocks a write wordline from toggling unless input data to be written to the row has a valid state or a write force signal is asserted. Moreover, output latch clocking may be blocked from toggling unless a row to be read stores a data word that has a valid state or the read force signal is asserted, and input latch clocking may also be blocked unless the input data to be written has a valid state or the write force signal is asserted.
摘要翻译：在根据有效/无效状态对每行进行限定的数组中，每行可以包括有效门控读取电路，以有条件地阻止读取字线切换，除非该行存储具有有效状态或读取强制信号的数据字被断言。此外，在写入操作中，每行可以具有有效门控写入电路，其有条件地阻止写入字线切换，除非要写入行的输入数据具有有效状态或写入强制信号被断言。此外，除非要读取的行存储具有有效状态的数据字或读取强制信号被断言，否则输出锁存时钟可能被阻止，并且输入锁存时钟也可能被阻塞，除非要写入的输入数据具有有效状态或写力信号被断言。

8. 发明申请

WO2016048660A1 VOLTAGE LEVEL SHIFTED SELF-CLOCKED WRITE ASSISTANCE 审中-公开
标题翻译：电压水平变化自锁写入辅助
公开(公告)号：WO2016048660A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/049220
申请日：2015-09-09
申请人： QUALCOMM INCORPORATED
发明人： HOFF, David Paul , KULKARNI, Amey , MARTZLOFF, Jason Philip , LILES, Stephen Edward
IPC分类号： G11C11/419 , G11C7/12 , G11C5/14 , G11C7/10 , H03K19/017
CPC分类号： G11C7/12 , G11C5/14 , G11C7/1084 , G11C7/1093 , G11C7/1096 , G11C11/419 , H03K3/356104 , H03K3/35613 , H03K3/356139 , H03K3/356165 , H03K3/356173
摘要： Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals.
摘要翻译：用于产生电压电平转换的自记时写入辅助的系统和方法包括在第一电压域中具有自定时真实和补码数据输入信号的电路。第一和第二全电压电平移位器被配置为基于第一电压域中的自计时真实和补码数据输入信号，在第二电压域中产生电压电平移位的自适应中间真和互补信号。包括第一和第二互补金属氧化物半导体（CMOS）电路的三态逻辑被配置为基于电压电平来产生用于为第二电压域中的存储器阵列提供写入辅助的电压电平移位的自定时三态真和补输出信号改变了自己的时钟中间真实和补充信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式