专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2018044384A1 DATA STORAGE DEVICE ENCLOSURE 审中-公开
标题翻译：数据存储设备外壳
公开(公告)号：WO2018044384A1
公开(公告)日：2018-03-08
申请号：PCT/US2017/039341
申请日：2017-06-27
申请人： WESTERN DIGITAL TECHNOLOGIES, INC.
发明人： JENKINS, Dean Mitcham , RYAN, Robert P.
IPC分类号： G11B33/12 , G06F3/06
CPC分类号： G06F1/187 , G06F13/4022 , G06F13/4068 , G06F13/4282 , G11B33/126 , G11B33/128 , H05K7/1459 , H05K7/1488
摘要： A Data Storage Device (DSD) enclosure includes a chassis and at least one backplane mounted in the chassis. According to one aspect, each backplane includes a row of DSD slots and a switch slot located in a middle portion of the row of DSD slots. A plurality of signal traces connect the DSD slots to the switch slot.
摘要翻译：数据存储设备（DSD）机箱包括一个机箱和至少一个安装在机箱中的背板。根据一个方面，每个底板包括一排DSD插槽和位于该排DSD插槽的中间部分中的开关槽。多条信号线将DSD插槽连接到交换机插槽。

2. 发明申请

WO2014150918A1 IN-PACKAGE FLY-BY SIGNALING 审中-公开
标题翻译： IN-PACKAGE FLY-BY信号
公开(公告)号：WO2014150918A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/024534
申请日：2014-03-12
申请人： INVENSAS CORPORATION
发明人： CRISP, Richard, Dewitt , ZOHNI, Wael , HABA, Belgacem , CHEN, Yong
IPC分类号： G11C5/06 , H01L23/498 , H01L25/065 , H01L23/13 , H01L29/40 , H01L23/31
CPC分类号： H05K7/1459 , G11C5/063 , H01L23/13 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L25/0655 , H01L2224/4824 , H01L2924/15311
摘要： In-package fly by signaling can be provided in a multi-chip microelectronic package (100) having address lines (126) on a package substrate (102) configured to carry address information to a first connection region (126C) on the substrate having a first delay from terminals (120) of the package, and the address lines being configured to carry the address information beyond the first connection region (126C) to at least to a second connection region (126D) having a second delay from the terminals (120) that is greater than the first delay. Address inputs (140) of a first microelectronic element (110), e.g., semiconductor chip, can be coupled with each of the address lines at the first connection region (126C), and address inputs (140) of a second microelectronic element (112) can be coupled with each of the address lines at the second connection region (126D).
摘要翻译：通过信令的包装内飞行可以提供在具有在封装基板（102）上的地址线（126）的多芯片微电子封装（100）中，该封装基板（102）被配置为将地址信息传送到基板上的第一连接区域（126C）第一延迟来自封装的端子（120），并且地址线被配置为将地址信息超出第一连接区域（126C）传送至至少具有来自端子（120）的第二延迟的第二连接区域（126D））大于第一个延迟。第一微电子元件（110）的地址输入（140）（例如半导体芯片）可以与第一连接区域（126C）处的每个地址线和第二微电子元件（112）的地址输入（140）耦合）可以与第二连接区域（126D）处的每个地址线耦合。

3. 发明申请

WO2012159933A2 SERIAL LINK INTERCONNECTION ARRANGEMENT FOR BACKPLANE WITH EMBEDDED WAVEGUIDE 审中-公开
标题翻译：带有嵌入式波导的背板的串行链路互连布置
公开(公告)号：WO2012159933A2
公开(公告)日：2012-11-29
申请号：PCT/EP2012/058992
申请日：2012-05-15
申请人： ALCATEL LUCENT , HOOGHE, Koen
发明人： HOOGHE, Koen
IPC分类号： H05K1/14 , H05K1/02 , G06F13/40 , H05K7/14
CPC分类号： H05K1/14 , H01P5/103 , H05K1/0243 , H05K1/141 , H05K7/1459 , H05K2201/0311 , H05K2201/044 , H05K2201/10189
摘要： A serial link interconnection arrangement for interconnecting a first printed circuit board (BoardA) with a second printed circuit board (BoardB), both boards being inserted in a backplane of a telecommunication system. The arrangement comprises a waveguide embedded in the backplane. A first end (WavA) of the waveguide is coupled to the first board (BoardA) via a first connection system (ConA), whilst the second end (WavB) of the waveguide is coupled to the second board (BoardB) via a second connection system (ConB). Each of the connection systems (ConA; ConB) comprises a transceiver (IntA; IntB) adapted to convert a parallel signal received from the printed circuit board (BoardA; BoardB) into a serial stream transmitted to an end (WavA; WavB) of the waveguide via an antenna (AntA; AntB), and vice-versa.
摘要翻译：一种用于将第一印刷电路板（BoardA）与第二印刷电路板（BoardB）互连的串行链路互连装置，两个板插入电信系统的背板中。该布置包括嵌入背板中的波导。波导的第一端（WavA）通过第一连接系统（ConA）耦合到第一板（BoardA），而波导的第二端（WavB）通过第二连接耦合到第二板（BoardB）系统（ConB）。每个连接系统（ConA; ConB）包括适于将从印刷电路板（BoardA; BoardB）接收的并行信号转换成传输到端部（WavA; WavB）的串行流的收发器（IntA; IntB）波导通过天线（AntA; AntB），反之亦然。

4. 发明申请

WO2004031968A3 SINGLE SHELF ROUTER 审中-公开
标题翻译：单层路由器
公开(公告)号：WO2004031968A3
公开(公告)日：2007-10-18
申请号：PCT/US0330043
申请日：2003-09-25
申请人： AVICI SYSTEMS INC , GUNNER CHRIS , HAMILTON MARK
发明人： GUNNER CHRIS , HAMILTON MARK
IPC分类号： G06F15/173 , G06F13/40 , H04L12/56 , H05K7/14
CPC分类号： H04L45/583 , H05K7/1459
摘要： A fabric of modules includes a plurality of physically offset adjacent modules and first dimension links which, in at least one linear array of modules, connect single offset modules in a ring. The fabric also includes second dimension links which connect the modules of each linear array in at least one ring with substantially all links between modules in each array being double offset links bypassing a single module, and third dimension links which connect modules of each linear array in at least one ring with substantially all links between modules in each array being triple offset links bypassing two modules.
摘要翻译：模块的结构包括多个物理偏移的相邻模块和在至少一个线性阵列的模块中连接环中的单个偏移模块的第一维度链接。该织物还包括第二维度链接，其将至少一个环中的每个线性阵列的模块连接到每个阵列中的模块之间的基本上所有的链接，其中双重偏移链路绕过单个模块，以及第三维度链接，其将每个线性阵列的模块连接到至少一个环，其中每个阵列中的模块之间具有基本上所有的链路，其中三个偏移链路绕过两个模块。

5. 发明申请

WO2005093912A1 DISTRIBUTING AN ELECTRONIC SIGNAL IN A STACKABLE DEVICE 审中-公开
标题翻译：在可堆叠设备中分配电子信号
公开(公告)号：WO2005093912A1
公开(公告)日：2005-10-06
申请号：PCT/US2005/004214
申请日：2005-02-09
申请人： CISCO TECHNOLOGY, INC. , MOON, Bruce
发明人： MOON, Bruce
IPC分类号： H01R25/00
CPC分类号： H05K7/023 , G06F13/4095 , H05K7/1459
摘要： Techniques are provided for distributing signals in a stackable unit (101A, 101B, 101C), including a first input connector (120J) of two ore more input connectors; a second input connector (120K) of two or more input connectors, wherein the first input connector is spaced apart form the second input connector, and the first input connector has a particular spatial relationship to the second input connector; a first output connector (110J) of two or more output connectors; a second output connector (110K) of two or more output connectors, wherein the first output connector is spaced apart form the second output connector, and the first output connector has the same particular spatial relationship to the second output connector; means for communicatively coupling the first input connector and the second output connector; and mean for terminating the first output connector.
摘要翻译：提供了用于在可堆叠单元（101A，101B，101C）中分配信号的技术，包括两个以上输入连接器的第一输入连接器（120J）两个或多个输入连接器的第二输入连接器（120K），其中所述第一输入连接器从所述第二输入连接器间隔开，并且所述第一输入连接器与所述第二输入连接器具有特定的空间关系; 两个或多个输出连接器的第一输出连接器（110J）; 两个或多个输出连接器的第二输出连接器（110K），其中所述第一输出连接器从所述第二输出连接器间隔开，并且所述第一输出连接器与所述第二输出连接器具有相同的特定空间关系; 用于通信地耦合第一输入连接器和第二输出连接器的装置; 并意味着终止第一输出连接器。

6. 发明申请

WO0180574B1 SPLITTER ARCHITECTURE FOR A TELECOMMUNICATION SYSTEM 审中-公开
标题翻译：电信系统分裂结构
公开(公告)号：WO0180574B1
公开(公告)日：2002-05-23
申请号：PCT/US0111494
申请日：2001-04-09
申请人： ADC TELECOMMUNICATIONS INC
发明人： SWAM STEVEN M , SIT ERIC K , MORGENSTERN TODD A
IPC分类号： H04Q1/10 , H04Q1/14 , H05K1/11 , H05K1/14 , H05K7/14
CPC分类号： H05K7/1459 , H04Q1/028 , H04Q1/10 , H04Q1/14 , H04Q1/155 , H04Q2201/12 , H04Q2201/802 , H05K1/0295 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10356
摘要： An interface card (42) adapted to be mounted at the back plane (46) of a splitter chassis (44). The interface card includes card edge connectors (60, 62) for providing connections with a splitter card. The interface card (44) also includes cable connectors (54, 56, 58) for inputting mixed voice and data, and for outputting data and voice signals. Tracings (76, 84, 88, 80) are provided on the interface card for interconnecting the cable connectors and the card edge connectors. The tracings are configured such that first tracings carrying data signals from the splitter card to the cable connectors do not cross second tracings carrying voice signals form the splitter card to the cable connectors.
摘要翻译：接口卡（42）适用于安装在分线器底盘（44）的底板（46）上。接口卡包括用于提供与分离器卡连接的卡边缘连接器（60,62）。接口卡（44）还包括电缆连接器（54,56,58），用于输入混合的语音和数据，并用于输出数据和语音信号。在接口卡上提供迹线（76,84,88,80），用于互连电缆连接器和卡边缘连接器。迹线被配置为使得从分离卡传送数据信号到电缆连接器的第一迹线不会跨越将来自分离器卡的语音信号的第二迹线穿过到电缆连接器。

7. 发明申请

WO99017404A1 HIGH FREQUENCY BUS SYSTEM 审中-公开
标题翻译：高频总线系统
公开(公告)号：WO99017404A1
公开(公告)日：1999-04-08
申请号：PCT/US1998/019837
申请日：1998-09-22
IPC分类号： G06F13/00 , G06F13/40 , G11C5/00 , G11C5/06 , H05K1/02 , H05K1/14 , H05K7/14 , H01R9/09
CPC分类号： G11C5/063 , G06F13/1684 , G06F13/4086 , G06F13/409 , G06F13/4247 , G11C5/04 , G11C7/1048 , H05K1/023 , H05K1/0246 , H05K1/0248 , H05K1/14 , H05K7/1459 , H05K2201/044 , H05K2201/09263 , H05K2201/10022 , H05K2201/10159 , H05K2201/10689
摘要： A high frequency bus system (450) which insures uniform arrival times of high fidelity signals to the devices (510), despite the use of the bus (450) on modules (420) and connectors. The high frequency bus system (450) includes a first bus segment having one or more devices (510) connected between a first and second end. The high frequency bus system (450) also includes a second bus segment which has no devices connected to it. The first end of the first segment and the second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at substantially the same time, they arrive at each device (510) connected to the first bus segment at substantially the same time. Conversely when two signals originate at a device (510) substantially at the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data, or control, carried by the signals.
摘要翻译：尽管在模块（420）和连接器上使用总线（450），但是高频总线系统（450）确保高保真信号到达设备（510）的均匀到达时间。高频总线系统（450）包括具有连接在第一和第二端之间的一个或多个设备（510）的第一总线段。高频总线系统（450）还包括没有与其连接的设备的第二总线段。第一段的第一端和第二段的第二端串联耦合以形成一段链段，并且当两个信号在基本上同时被引入第二总线段的第一端时，它们到达每个设备（510）基本上同时连接到第一总线段。相反，当两个信号基本上在同一时间发生在设备（510）时，它们在几乎相同的时间到达第二总线段的第一端。尽管使用连接器将段连接在一起，尽管分段位于模块上，而不需要存根，尽管存在段中的路由转换，并且尽管存在诸如地址，数据的信息类型，但是均匀到达时间成立，或由信号承载的控制。

8. 发明申请

WO1998020585A1 ADAPTIVE MODEM APPARATUS 审中-公开
标题翻译：自适应调制解调器
公开(公告)号：WO1998020585A1
公开(公告)日：1998-05-14
申请号：PCT/US1997016038
申请日：1997-09-10
申请人： PARADYNE CORPORATION
发明人： PARADYNE CORPORATION , GEORGOPULOS, Thomas
IPC分类号： H01R25/00
CPC分类号： H05K7/1459 , H01R12/721 , H01R31/06 , H01R2201/16
摘要： An adaptive modem apparatus which allows a single modem (34) to be utilized alternatively in either stand-alone, external fashion, or internally. The modem (34) has an integrated circuit board (49) with an edge connector (38) defining a plurality of first electrical contacts (53), and an adapter (40). The adapter (40) has both a first and second electrical connectors (70, 75). The first electrical connector (70) is defined by a slot configured to releasably engage the edge connector (38), and further includes a plurality of electrical contacts (72) disposed to align with the electrical contacts (53). The second electrical connector (75) is defined by a D-shaped shell and has a plurality of electrical contacts (76) that are electrically interconnected with the plurality of contacts (72). In use, the adpater (40) may be readily attached to the edge connector (38) so that the modem (34) may be connected to a computer (10) and utilized in a stand-alone configuration. Moreover, the adapter (40) may be readily detached from the edge connector (38) so that the modem (34) may be connected to a motherboard edge connector (86) and utilized as an internal modem.
摘要翻译：一种自适应调制解调器装置，其允许单独的调制解调器（34）以独立的，外部的方式或内部地交替使用。调制解调器（34）具有集成电路板（49），其具有限定多个第一电触点（53）的边缘连接器（38）和适配器（40）。适配器（40）具有第一和第二电连接器（70,75）。第一电连接器（70）由构造成可释放地接合边缘连接器（38）的槽限定，并且还包括多个设置成与电触点（53）对准的电触头（72）。第二电连接器（75）由D形壳体限定，并且具有与多个触头（72）电互连的多个电触点（76）。在使用中，接收器（40）可以容易地附接到边缘连接器（38），使得调制解调器（34）可以连接到计算机（10）并且以独立配置来使用。此外，适配器（40）可以容易地从边缘连接器（38）分离，使得调制解调器（34）可以连接到母板边缘连接器（86）并用作内部调制解调器。

9. 发明申请

WO2016151053A1 CARTE ÉLECTRONIQUE DE FOND DE PANIER ET CALCULATEUR ÉLECTRONIQUE ASSOCIÉ 审中-公开
标题翻译：背板电子板及相关电子控制单元
公开(公告)号：WO2016151053A1
公开(公告)日：2016-09-29
申请号：PCT/EP2016/056462
申请日：2016-03-23
申请人： SAFRAN ELECTRONICS & DEFENSE
发明人： GUILLOT, François , SPOOR, Pascal , CHETANNEAU, Patrice
IPC分类号： H05K1/02 , H05K7/14 , H05K3/00
CPC分类号： H05K7/1439 , G06F1/184 , H01R12/7064 , H01R12/716 , H05K1/111 , H05K1/115 , H05K3/0011 , H05K3/0094 , H05K3/421 , H05K3/4644 , H05K7/1412 , H05K7/1445 , H05K7/1452 , H05K7/1459 , H05K2201/0104 , H05K2201/09509 , H05K2201/09545 , H05K2201/10189 , H05K2201/10295
摘要： La présente invention concerne une carte électronique de fond de panier (20) présentant une face interne (142) adaptée pour être connectée à des connecteurs de cartes électroniques (12) et une face externe (143) adaptée pour être connectée à un connecteur externe (15), la carte de fond de panier (20) étant caractérisée en ce qu'elle présente des trous borgnes débouchant sur sa face interne (142), et des trous débouchant sur sa face externe (143), les trous étant adaptés pour recevoir des éléments de connexion à insertion par force et former avec eux un point de connexion électrique.
摘要翻译：本发明涉及一种背板电子板（20），其具有适于连接到电子板连接器（12）的内表面（142）和适于连接到外连接器（15）的外表面（143），所述背板其特征在于，具有在其内表面（142）上开口的盲孔和在其外表面（143）上开口的孔，该孔适于接收压配合连接元件并形成电连接点。

10. 发明申请

WO2009136816A1 BACKPLANE NETWORK DISTRIBUTION 审中-公开
标题翻译： BACKPLANE网络分配
公开(公告)号：WO2009136816A1
公开(公告)日：2009-11-12
申请号：PCT/SE2008/000310
申请日：2008-05-07
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) , RIMBORG, Mats
发明人： RIMBORG, Mats
IPC分类号： H05K7/14 , G06F13/40 , H04L12/56
CPC分类号： H05K7/1459 , G06F13/409 , Y02D10/14 , Y02D10/151
摘要： A backplane arrangement 200; 500 and method for distributing network connections in said backplane arrangement 200; 500 comprising a number of board positions Ac-Fc; Gc-Kc each arranged to operatively receive a board Ab-Fb; Gb-Kb, and a backplane- network arrangement 250, 300; 550, 600, 600' arranged to operatively make a plurality of network connections a-n; a-g available at a first board position Ac; Gc. The backplane arrangement 200; 500 is characterized in f/?af a first allocation arrangement Aen1-Aen14; Gen8-Gen14 is arranged to operatively allocate a set of the available network connections a-n; a-g to be used by a board Ab received in the first board position Ac; Gc; and a first bypass arrangement Ap; Aps; Aps'; Gp is arranged to operatively bypass a set of the available network connections b-n; b-g unallocated at the first board position Ac; Gc to a second subsequent board position Bc; Hc via the backplane-network arrangement 250; 550.
摘要翻译：背板装置200; 500和用于在所述背板装置200中分配网络连接的方法; 500包含多个板位置Ac-Fc; Gc-Kc各自布置成可操作地接收板Ab-Fb; Gb-Kb和背板网络布置250,300; 550,600,600'，用于可操作地使多个网络连接a-n; a-g可在第一板位置Ac; GC。背板装置200; 500的特点是f /？af第一次分配安排Aen1-Aen14; Gen8-Gen14被布置成可操作地分配一组可用网络连接a-n; a-g被董事会使用Ab获得在第一板位置Ac; GC; 和第一旁路装置Ap; APS; APS'; Gp被布置成可操作地绕过一组可用网络连接b-n; b-g未分配在第一板位置Ac; Gc到第二个后续的董事会职位Bc; Hc通过背板网络布置250; 550。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式