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1. 发明申请

WO2004062111A1 HIGH SPEED TURBO CODES DECODER FOR 3G USING PIPELINED SISO LOG-MAP DECODERS ARCHITECTURE 审中-公开
标题翻译：使用流水线SISO LOG-MAP解码器架构的3G高速Turbo码解码器
公开(公告)号：WO2004062111A1
公开(公告)日：2004-07-22
申请号：PCT/US2003/035865
申请日：2003-11-07
申请人： ICOMM TECHNOLOGIES, INC.
发明人： NGUYEN, Quang
IPC分类号： H03M13/00
CPC分类号： H03M13/3927 , H03M13/2771 , H03M13/2987 , H03M13/3905 , H03M13/3922 , H03M13/3961 , H03M13/6306 , H03M13/6563 , H04L1/005 , H04L1/0052 , H04L1/0054 , H04L1/0055 , H04L1/0066 , H04L1/0071
摘要： The invention encompasses several improved Turbo Codes Decoder method and apparatus to provide a more suitable, practical and simpler method for implementing a Turbo Codes Decoder in ASIC or DSP codes. (1) Two Parallel Turbo Codes Decoder blocks (40A & 40B) to compute soft-decoded data RXDa, RXDb from two different received path. (2) Two pipelined Log-MAP decoders (A42 & B44) are used for iterative decoding received data. (3) A Sliding Window of block N data are used on the input memory for pipeline operations. (4) The output Block N Data from the first decoder A are stored in the RAM memory A, and the second decoder B stores output data in the RAM memory B while the decoder B decodes block N data from RAM memory A at the same clock cycle. (5) Log-Map decoders are simpler to implement and are low-power consumption. (6) Pipelined log-Map decoder’s architecture provides high-speed data throughout, one output per clock cycle.
摘要翻译：本发明包括若干改进的Turbo码解码器方法和装置，以提供用于在ASIC或DSP码中实现Turbo码解码器的更合适，实用和更简单的方法。（1）两个并行Turbo码解码器块（40A和40B），以从两个不同的接收路径计算软解码数据RXDa，RXDb。（2）使用两个流水线Log-MAP解码器（A42和B44）迭代解码接收到的数据。（3）在输入存储器上使用块N数据的滑动窗口进行流水线操作。（4）来自第一解码器A的输出块N数据存储在RAM存储器A中，第二解码器B将输出数据存储在RAM存储器B中，而解码器B在同一时钟解码来自RAM存储器A的块N数据周期。（5）Log-Map解码器更易于实现并且功耗低。（6）流水线日志 - 地图解码器的架构提供了高速数据，每个时钟周期一个输出。

2. 发明申请

WO2004062111A9 HIGH SPEED TURBO CODES DECODER FOR 3G USING PIPELINED SISO LOG-MAP DECODERS ARCHITECTURE 审中-公开
标题翻译：用于3G的高速涡轮编码解码器使用管道SISO LOG-MAP解码器架构
公开(公告)号：WO2004062111A9
公开(公告)日：2004-08-26
申请号：PCT/US0335865
申请日：2003-11-07
申请人： ICOMM TECHNOLOGIES INC
发明人： NGUYEN QUANG
IPC分类号： H03M13/29 , H04L1/00 , H03M13/00
CPC分类号： H03M13/3927 , H03M13/2771 , H03M13/2987 , H03M13/3905 , H03M13/3922 , H03M13/3961 , H03M13/6306 , H03M13/6563 , H04L1/005 , H04L1/0052 , H04L1/0054 , H04L1/0055 , H04L1/0066 , H04L1/0071
摘要： The invention encompasses several improved Turbo Codes Decoder method and apparatus to provide a more suitable, practical and simpler method for implementing a Turbo Codes Decoder in ASIC or DSP codes. (1) Two Parallel Turbo Codes Decoder blocks (40A & 40B) to compute soft-decoded data RXDa, RXDb from two different received path. (2) Two pipelined Log-MAP decoders (A42 & B44) are used for iterative decoding received data. (3) A Sliding Window of block N data are used on the input memory for pipeline operations. (4) The output Block N Data from the first decoder A are stored in the RAM memory A, and the second decoder B stores output data in the RAM memory B while the decoder B decodes block N data from RAM memory A at the same clock cycle. (5) Log-Map decoders are simpler to implement and are low-power consumption. (6) Pipelined log-Map decoder's architecture provides high-speed data throughout, one output per clock cycle.
摘要翻译：本发明包括几种改进的Turbo码解码器方法和装置，以提供用于在ASIC或DSP代码中实现Turbo码解码器的更合适，实用和更简单的方法。（1）两个并行Turbo码解码器块（40A和40B），用于从两个不同的接收路径计算软解码数据RXDa，RXDb。（2）两条流水线Log-MAP解码器（A42和B44）用于迭代解码接收数据。（3）在输入存储器中使用块N数据的滑动窗口进行管道操作。（4）来自第一解码器A的输出块N数据被存储在RAM存储器A中，并且第二解码器B将输出数据存储在RAM存储器B中，而解码器B在相同的时钟解码来自RAM存储器A的块N数据周期。（5）Log-Map解码器实现起来更简单，功耗更低。（6）流水线对数映射解码器的架构提供高速数据，每个时钟周期有一个输出。

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