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1. 发明申请

WO2016010631A1 WIDEBAND LOW-POWER AMPLIFIER 审中-公开
标题翻译：宽带低功率放大器
公开(公告)号：WO2016010631A1
公开(公告)日：2016-01-21
申请号：PCT/US2015/032261
申请日：2015-05-22
申请人： QUALCOMM INCORPORATED
发明人： ARCUDIA, Kenneth Luis , CHEN, Zhiqin
IPC分类号： H03F3/45 , H03F1/42 , H03F1/32
CPC分类号： H03F1/3211 , H03F1/42 , H03F3/45197 , H03F3/45654 , H03F2203/45332 , H03F2203/45488 , H03F2203/45494 , H03F2203/45644 , H03F2203/45691 , H03F2203/45726 , H03G5/28
摘要： An amplifier (200) is provided that includes a differential pair of transistors (M1, M2) configured to steer a tail current responsive to a differential input voltage (inp, inm). The amplifier (200) also includes a transconductor (P4, P6) that tranconducts high-frequency changes in the differential output voltage (outp, outm) into a differential bias current conducted through the differential pair of transistors (M1, M2).
摘要翻译：提供了一种放大器（200），其包括构造成响应于差分输入电压（inp，inm）引导尾部电流的差分对晶体管（M1，M2）。放大器（200）还包括跨导（P4，P6），其将差分输出电压（outp，outm）中的高频变化转换成通过差分对晶体管（M1，M2）传导的差分偏置电流。

2. 发明申请

WO02017402A2 WIDEBAND DIFFERENTIAL AMPLIFIER AND SUMMING CIRCUIT INCLUDING SUCH WIDEBAND DIFFERENTIAL AMPLIFIER 审中-公开
标题翻译：宽带差分放大器和包括放大器的计算机电路
公开(公告)号：WO02017402A2
公开(公告)日：2002-02-28
申请号：PCT/US2001/022610
申请日：2001-08-21
IPC分类号： H01L27/07 , H01L27/08 , H03F3/30 , H03F3/45
CPC分类号： H01L27/0794 , H01L27/0802 , H01L27/0805 , H03F3/3023 , H03F3/3062 , H03F3/45188 , H03F3/45654 , H03F2203/30147 , H03F2203/45418 , H03F2203/45424 , H03F2203/45508 , H03F2203/45526
摘要： There is described a wideband fully differential amplifier (50) comprising inverting and non-inverting inputs, a common mode voltage terminal, and inverting and non-inverting outputs. This differential amplifier further comprises first and second parasitically compensated semiconductor resistors (521, 522) respectively connected between the non-inverting output and the inverting input, and between the inverting output and the non-inverting input of the amplifier.These first and second parasitically compensated semiconductor resistors each comprise a first conductive layer capacitively coupled to a semiconductor substrate and connected between the input and output of the differential amplifier; and a second conductive layer capacitively coupled to the first conductive layer and connected to the output of the differential amplifier.There is also described a summing circuit (40) including such a differential amplifier as well as a CD-ROM or DVD-ROM optical pickup device.
摘要翻译：全差分宽带放大器（50）包括反相和非反相输入，共模电压端，以及反相和非反相输出。差分放大器还包括第一和第二寄生半导体电阻器（521,522）。这些电阻分别连接在放大器的非反相输出端和反相输入端之间，以及该放大器的反相输出端和非反相输入端之间。所述第一和第二寄生半导体电阻器各自包括电容耦合到半导体衬底并连接在差分放大器的输入和输出之间的第一导电层以及第二层导体电容耦合到第一导电层并连接到所述差分放大器的输出。本发明还涉及包括该差分放大器和光学捕获设备CD-ROM或DVD-ROM的求和电路（40）。

3. 发明申请

WO2010099183A1 FAST COMMON MODE FEEDBACK CONTROL FOR DIFFERENTIAL DRIVER 审中-公开
标题翻译：用于差分驱动器的快速共同模式反馈控制
公开(公告)号：WO2010099183A1
公开(公告)日：2010-09-02
申请号：PCT/US2010/025208
申请日：2010-02-24
申请人： STANDARD MICROSYSTEMS CORPORATION , BELL, Marshall J.
发明人： BELL, Marshall J.
IPC分类号： H03F3/45 , H04L25/02
CPC分类号： H03F3/45179 , H03F3/45654 , H03F2200/453 , H03F2200/456 , H03F2200/78 , H03F2203/45008 , H03F2203/45074 , H03F2203/45292 , H03F2203/45418 , H03F2203/45424 , H03F2203/45631 , H04L25/0276
摘要： A system and method for a fast stabilizing output buffer. A differential driver circuit is provided with an amplifier stage for receiving a differential input signal and generating a differential output based upon the input signal. The differential output has a corresponding common-mode (CM) voltage level typically based upon a value half of the power supply. A common-mode feedback buffer (CMFB) stage detects a change in the CM voltage level and recovers the CM voltage level to its desired value within a very fast settling time based upon a very high bus frequency. The CMFB stage utilizes a topology comprising only a single device. In one embodiment, this single device is a nmos transistor utilized as a transimpedance stage. Stability is provided by a circuit biasing stage and a shunting capacitor within the CMFB stage.
摘要翻译：用于快速稳定输出缓冲器的系统和方法。差分驱动器电路具有用于接收差分输入信号并基于输入信号产生差分输出的放大器级。差分输出具有通常基于电源的一半值的对应的共模（CM）电压电平。共模反馈缓冲器（CMFB）级检测CM电压电平的变化，并且基于非常高的总线频率在非常快的建立时间内将CM电压电平恢复到其期望值。 CMFB阶段使用仅包含单个设备的拓扑。在一个实施例中，该单个器件是用作跨阻抗级的nmos晶体管。稳定性由CMFB级内的电路偏置级和分流电容提供。

4. 发明申请

WO1997005696A1 FULLY DIFFERENTIAL OUTPUT CMOS POWER AMPLIFIER 审中-公开
标题翻译：全差分输出CMOS功率放大器
公开(公告)号：WO1997005696A1
公开(公告)日：1997-02-13
申请号：PCT/US1996012238
申请日：1996-07-24
申请人： INFORMATION STORAGE DEVICES, INC.
发明人： INFORMATION STORAGE DEVICES, INC. , TRAN, Hieu, Van
IPC分类号： H03F03/45
CPC分类号： H03F3/3001 , G05F3/242 , H03F3/3037 , H03F3/45192 , H03F3/45479 , H03F3/45654 , H03F2203/45418 , H03F2203/45424
摘要： A fully differential output CMOS power amplifier suitable to be used in a non-volatile memory mixed mode chip for voice record and playback to drive a very low impedance load such as an 8-ohm speaker from a low voltage supply. This fully differential CMOS power amplifier utilizes a voltage multiplying technique for the input stage (MN2, MN3, MP6, MP7), a level shift/gain stage (MN/P12, MN/P13), and a common mode feedback network (MN1, MN10, MP10). It also utilizes native n-MOS having a threshold voltage VT = 0v for the folded cascode differential input and the source follower output stage (MN7), enhancement n-MOS (VT = 0.7v) for the common source output, and a voltage regulator (22) using p-MOS diode connected devices (M1-M5) for simulating a resistor divider to regulate the voltage multiplier output. The amplifier also includes a mechanism for crossover distortion reduction at the output driver stage, and a scheme to set the idle current in the output driver n-MOS transistors (MN7, MN9).
摘要翻译：全差分输出CMOS功率放大器适用于非易失性存储器混合模式芯片，用于语音记录和重放，以从低压电源驱动非常低的阻抗负载，如8欧姆扬声器。该全差分CMOS功率放大器利用输入级（MN2，MN3，MP6，MP7），电平移位/增益级（MN / P12，MN / P13）和共模反馈网络（MN1， MN10，MP10）。它还利用对于共用源输出的折叠共源共栅差分输入和源极跟随器输出级（MN7），增强型n-MOS（VT = 0.7v）的阈值电压VT = 0v的本地n-MOS，以及电压调节器（22）使用p-MOS二极管连接的器件（M1-M5）来模拟电阻分压器来调节电压倍增器输出。放大器还包括用于在输出驱动级的交叉失真减小的机制，以及设置输出驱动器n-MOS晶体管（MN7，MN9）中的空闲电流的方案。

5. 发明申请

WO1997003496A1 CASCODE OPERATIONAL AMPLIFIER WITH MULTIPLE INPUT STAGE 审中-公开
标题翻译：具有多个输入级的CASCODE操作放大器
公开(公告)号：WO1997003496A1
公开(公告)日：1997-01-30
申请号：PCT/US1996002822
申请日：1996-03-01
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , HWANG, Chien-Meen , GERSHON, Eugen
IPC分类号： H03F03/45
CPC分类号： H03F3/4521 , H03F3/45188 , H03F3/45192 , H03F3/4565 , H03F3/45654 , H03F2203/45578
摘要： Disclosed herein is a cascode operational amplifier design with multiple input stages, and methods of operating the same, resulting in enhanced output gain and unity gain bandwidth operational amplifiers. The cascode operational amplifier comprises a differential input block which receives a differential input having a first differential input stage and a second differential input stage. A cascode block is coupled to the differential input block and provides a differential output for the operational amplifier. A common mode feedback block coupled to the second differential input stage of the differential input block and the differential output of the cascode block stabilizes a DC output level for the differential output. A load block is coupled to the differential output of the cascode block and applies a resistive load to the differential output in response to a differential input signal applied to the differential input block.
摘要翻译：这里公开了具有多个输入级的共源共栅运算放大器设计及其操作方法，导致增强的输出增益和单位增益带宽运算放大器。共源共栅运算放大器包括差分输入块，其接收具有第一差分输入级和第二差分输入级的差分输入。共源共栅块耦合到差分输入块，并为运算放大器提供差分输出。耦合到差分输入块的第二差分输入级的共模反馈块和共源共栅组的差分输出稳定用于差分输出的DC输出电平。负载块耦合到共源共栅块的差分输出，并响应于施加到差分输入块的差分输入信号，向差分输出施加电阻性负载。

6. 发明申请

WO2012029078A3 LOW DISTORTION FILTERS 审中-公开
标题翻译：低失真滤波器
公开(公告)号：WO2012029078A3
公开(公告)日：2012-04-26
申请号：PCT/IN2011000601
申请日：2011-09-02
申请人： SECRETARY DEPT OF INFORMATION TECHNOLOGY DIT , INDIAN INST TECHNOLOGY MADRAS , PAVAN YENDLURI SHANTHI , THYAGARAJAN SIVA VISWANATHAN
发明人： PAVAN YENDLURI SHANTHI , THYAGARAJAN SIVA VISWANATHAN
IPC分类号： H03F1/32 , H03H11/00
CPC分类号： H03H11/02 , H03F3/211 , H03F3/45192 , H03F3/45654 , H03F2200/405 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2203/45418 , H03F2203/45424 , H03F2203/45512 , H03F2203/45526 , H03F2203/45528 , H03F2203/45594 , H03F2203/45702
摘要： An integrated continuous-time active-RC filter comprises a set of opamp integrators with Operational Transconductance Amplifiers (OTAs). The filter further includes at least one assistant connected between the input and output of each of the integrators of the set to enhance the linearity and speed of the opamp integrators of the set. The assistant comprises a plurality of sets of transconductors connected in parallel to each other wherein each set of transconductors is formed by a pair of MOSFETs connected in series, with one MOSFET operating in the triode region and the other MOSFET operating in the saturation region. The assistant is configured to provide an assistant current to be injected into the source of each of the integrators in the set to enhance the linearity and speed of the opamp integrators of the set.
摘要翻译：集成的连续时间有源RC滤波器包含一组带运算跨导放大器（OTA）的运算放大器集成电路。该滤波器还包括至少一个连接在该组中每个积分器的输入和输出之间的助手，以增强该组的运算放大器积分器的线性度和速度。该助手包括彼此并联连接的多组跨导体，其中每组跨导体由一对串联连接的MOSFET形成，其中一个MOSFET在三极管区中操作，另一个MOSFET在饱和区中操作。该助理被配置成提供辅助电流以注入该组中的每个积分器的源中以增强该组的运算放大器积分器的线性度和速度。

7. 发明申请

WO2009092475A3 METHOD AND APPARATUS FOR IMPROVEMENT OF MATCHING FET CURRENTS USING A DIGITAL TO ANALOG CONVERTER 审中-公开
标题翻译：使用数字到模拟转换器改善匹配FET电流的方法和装置
公开(公告)号：WO2009092475A3
公开(公告)日：2010-02-04
申请号：PCT/EP2008065828
申请日：2008-11-19
申请人： IBM , IBM UK , BAUMGARTNER STEVEN JOHN , SILJENBERG DAVID , WOESTE DANA MARIE
发明人： BAUMGARTNER STEVEN JOHN , SILJENBERG DAVID , WOESTE DANA MARIE
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45654 , H03F3/45659 , H03F2203/45008 , H03F2203/45082 , H03F2203/45342 , H03F2203/45354 , H03F2203/45418 , H03F2203/45438 , H03F2203/45588 , H03F2203/45616 , H03F2203/45681
摘要： A method, apparatus and design structure to equalize currents on a matching pair of FETs having sources connected together on a silicon on insulator semiconductor chip, or other chip wherein FET bodies can be individually biased. During a determination period, functional inputs coupled to the gates of the matching pair of FETs are short circuited, and a DAC adjusts a first body voltage of a first FET in the matching pair of FETs relative to a second body voltage of a second FET in the matching pair of FETs until a currents in the first FET and the second FET are equal, within resolution of the DACs voltage granularity. A proper DAC control value is stored and applied to the DAC following the determination period when the short circuit is removed from the functional inputs.
摘要翻译：一种在绝缘体上半导体芯片上连接在一起的源的匹配对的一对FET或其它FET体可以被单独偏置的其他芯片的电流均衡的方法，装置和设计结构。在确定期间，耦合到匹配的一对FET的栅极的功能输入短路，并且DAC相对于第二FET的第二体电压调整匹配的一对FET中的第一FET的第一体电压在DAC电压粒度的分辨率内，直到第一FET和第二FET中的电流相等的匹配的一对FET。在从功能输入断开短路的确定周期之后，将适当的DAC控制值存储并应用于DAC。

8. 发明申请

WO0213377A3 A SWITCHED-CAPACITOR, COMMON-MODE FEEDBACK CIRCUIT FOR A DIFFERENTIAL AMPLIFIER WITHOUT TAIL CURRENT 审中-公开
标题翻译：用于不具有尾流电流的差分放大器的开关电容器，通用反馈电路
公开(公告)号：WO0213377A3
公开(公告)日：2003-11-06
申请号：PCT/US0141576
申请日：2001-08-03
申请人： BROADCOM CORP
发明人： KWAN TOM W , SINGOR FRANK , DUNCAN RALPH
IPC分类号： H03F3/00 , H03F3/45
CPC分类号： H03F3/45645 , H03F3/005 , H03F3/45179 , H03F3/45188 , H03F3/45654 , H03F2203/45394 , H03F2203/45421 , H03F2203/45651
摘要： Provided is a switched capacitor feedback circuit including two or more input ports configured to receive a corresponding a number of input signals and at least one output port. The output port is configured to output an adjusting signal. The input signals includes a number of primary signals and two or more reference signals that are associated with a first timing phase of operation. The adjusting signal is produced based upon a comparison between the primary signals the reference signals. Also provided is a pair of active devices having gates coupled together and structured to receive the adjusting signal. The active devices are configured to provide a gain to the adjusting signal in accordance with a predetermined gain factor, and facilitate an adjustment to the number of primary signals based upon the gain during a second timing phase of operation.
摘要翻译：提供了一种开关电容器反馈电路，其包括被配置为接收对应的多个输入信号和至少一个输出端口的两个或多个输入端口。输出端口配置为输出调整信号。输入信号包括与第一定时相位相关联的多个主信号和两个或更多个参考信号。基于主信号之间的参考信号的比较产生调整信号。还提供了一对具有耦合在一起并被构造成接收调节信号的门的有源器件。有源器件被配置为根据预定的增益因子向调整信号提供增益，并且有助于在操作的第二定时阶段期间基于增益来调整主信号的数量。

9. 发明申请

WO02052720A3 CIRCUIT FOR LOW NOISE, FULLY DIFFERENTIAL AMPLIFICATION 审中-公开
标题翻译：电路低噪声全差分增益
公开(公告)号：WO02052720A3
公开(公告)日：2003-02-27
申请号：PCT/EP0114288
申请日：2001-12-05
申请人： INFINEON TECHNOLOGIES AG , SCHIMPER MARKUS , MECHNIG STEPHAN , SCHLEDZ RALF
发明人： SCHIMPER MARKUS , MECHNIG STEPHAN , SCHLEDZ RALF
IPC分类号： H03F1/26 , H03F3/45
CPC分类号： H03F3/45183 , H03F3/45654
摘要： The invention relates to a circuit for low noise, fully differential amplification. A feedback signal (121) is detected in a differential output step of the differential amplification circuit by means of a voltage distributor formed by a first feedback resistance (119) and a second feedback resistance (120). A first output signal (111) is provided at a first output circuit node (117) and a second output signal (112) is provided at a second output circuit node (118). The respective first and second output signals (111) or (112) form a full output signal which corresponds to an input signal formed by a first and a second input signal (101) or (102). A load current (134), an input current (132) and a reference current (132) are established by means of a load current source (128), an input current source (131) and a reference current source (127). A matching transistor (301) is used to adjust an adaptation between the load current source (128), the input current source (131) and the reference current source (127). A feedback signal (121) of the differential amplification circuit is compared with a reference voltage (122) in a reference step, and the load current (134) is mirrored in the differential input step, in a current mirror device.
摘要翻译：本发明提供一种低噪声全差分放大，其特征在于，使用第一反馈电阻器（119）和形成的第二反馈电阻电压分配器（120）中的一个的反馈信号（121）设置在所述差动放大器电路的差分输出级确定的电路布置。的第一输出信号（111）在第一输出节点（117）被提供，而在第二输出节点（118）提供的第二输出信号（112）。相应的第一和第二输出信号（111）和（112）形成对应于第一和第二输入信号（101）和（102）的输入信号的复合的整体输出信号。由负载电流源（128）的装置，输入功率源（131）和参考电流源（127）在每种情况下确定的Laststom（134）的输入电流（132）和一个参考电流（133）。调整晶体管（301）是负载电流源（128），所述Eingangssromquelle（131）和所述参考电流源（127）之间的匹配的设定。在一个Refernzstufe差分放大器电路的反馈信号（121）与参考电压（122），并在电流镜装置相比，负载电流（134）在所述差分输入级被镜像。

10. 发明申请

WO2016099754A1 GAIN CONTROL IN COMPLEMENTARY COMMON GATE AND COMMON SOURCE AMPLIFIERS 审中-公开
标题翻译：补充共同门和普通源放大器的增益控制
公开(公告)号：WO2016099754A1
公开(公告)日：2016-06-23
申请号：PCT/US2015/061142
申请日：2015-11-17
申请人： QUALCOMM INCORPORATED
发明人： LIAO, Chih-Fan
IPC分类号： H03F1/02 , H03F3/193 , H03F3/26 , H03F3/45 , H03H11/32 , H03G3/30
CPC分类号： H03G3/3036 , H03F1/0272 , H03F1/0277 , H03F3/19 , H03F3/193 , H03F3/265 , H03F3/45654 , H03F2200/451 , H03F2200/54 , H03F2200/72 , H03F2200/75 , H03F2203/45228 , H03F2203/45731 , H03G1/0029 , H03G1/0088 , H03G3/3052
摘要： Gain control in complementary common gate and common source amplifiers is disclosed. In an exemplary embodiment, an apparatus includes a first amplifier stage (302) configured to amplify an input signal at an input terminal (316) to generate a first amplified signal (RF_OUTP). The first amplifier stage (302) includes a current diverter (702) that selectively diverts current to set a gain of the first amplifier stage (302). The apparatus also includes a second amplifier stage (304) configured to amplify the input signal at the input terminal (316) to generate a second amplified signal (RF_OUTN). The second amplifier stage (304) includes a gain control circuit (704) to set a gain of the second amplifier stage (304).
摘要翻译：公开了互补公共栅极和公共源极放大器中的增益控制。在示例性实施例中，一种装置包括：第一放大级（302），被配置为放大输入端（316）处的输入信号以产生第一放大信号（RF_OUTP）。第一放大器级（302）包括选择性地转移电流以设置第一放大器级（302）的增益的电流分流器（702）。该装置还包括被配置为放大输入端（316）处的输入信号以产生第二放大信号（RF_OUTN）的第二放大级（304）。第二放大级（304）包括用于设定第二放大级（304）的增益的增益控制电路（704）。

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