专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO1998018158A1 POLYSILICON PLUG SRAM LOAD 审中-公开
公开(公告)号：WO1998018158A1
公开(公告)日：1998-04-30
申请号：PCT/US1997008091
申请日：1997-05-12
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , WOLLESEN, Donald, L.
IPC分类号： H01L21/3205
CPC分类号： H01L28/20 , H01L21/76838 , H01L27/1112
摘要： A method of manufacturing a polysilicon plug in an integrated circuit semiconductor device wherein the polysilicon plug is selectively doped to act as a resistive load or alternatively to act as a diode load. The polysilicon load can be used in an SRAM memory cell.
摘要翻译：一种在集成电路半导体器件中制造多晶硅插塞的方法，其中多晶硅插塞被选择性地掺杂以充当电阻负载或替代地充当二极管负载。多晶硅负载可用于SRAM存储单元。

2. 发明申请

WO2009096000A1 半導体記憶装置审中-公开
标题翻译：半导体存储设备
公开(公告)号：WO2009096000A1
公开(公告)日：2009-08-06
申请号：PCT/JP2008/051303
申请日：2008-01-29
申请人：日本ユニサンティスエレクトロニクス株式会社 , 舛岡富士雄 , 新井紳太郎
发明人：舛岡富士雄 , 新井紳太郎
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , H01L27/1112
摘要：　縦型トランジスタＳＧＴで構成されたＥ／Ｒ型４Ｔ－ＳＲＡＭにおいて、小さいＳＲＡＭセル面積と安定した動作マージンを実現する。　４個のＭＯＳトランジスタ及び２個の負荷抵抗素子を用いて構成されたスタティック型メモリセルにおいて、前記メモリセルを構成するＭＯＳトランジスタは、埋め込み酸化膜上に形成された平面状シリコン層上に形成され、前記平面状シリコン層は記憶ノードであり、前記ＭＯＳトランジスタのドレイン、ゲート、ソースが垂直方向に配置され、ゲートが柱状半導体層を取り囲む構造を有し、負荷抵抗素子は前記平面状シリコン層上に形成されたポリシリコンプラグよりなる小さい面積のＳＲＡＭセルを実現する。
摘要翻译：在包括垂直型晶体管SGT的E / R型4T-SRAM中实现SRAM单元的小平面尺寸和稳定的操作裕度。在包括四个MOS晶体管和两个负载电阻元件的静态存储单元中，构成存储单元的MOS晶体管形成在形成于嵌入氧化层上的平面硅层上，该平面硅层是存储节点，并且该MOS晶体管具有栅极和源极沿垂直方向排列的结构，栅极包围柱状半导体层。此外，负载电阻元件包括形成在平面硅层上的多晶硅块，从而实现具有小平面尺寸的SRAM单元。

3. 发明申请

WO03023847A3 INTEGRATED CIRCUIT, PORTABLE DEVICE AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路，便携式设备及制造集成电路的方法
公开(公告)号：WO03023847A3
公开(公告)日：2003-10-02
申请号：PCT/IB0203628
申请日：2002-09-03
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： REINER JOACHIM C , GRADENWITZ PAUL G M
IPC分类号： H01L21/768 , H01L23/485 , H01L27/11 , H01L23/522
CPC分类号： H01L27/1112 , H01L21/76895 , H01L23/485 , H01L27/1108 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an integrated circuit, comprising: - a substrate with a first (semi-)conductive region arranged in or on the substrate; - a second (semi-)conductive region which is isolated for at least a considerable part relative to the first region and is arranged above or adjacent to the first region; - a third (semi-)conductive region which is insulated for at least a considerable part relative to the first and second (semi-)conductive regions and is arranged thereabove; - a fourth (semi-)conductive region which is insulated relative to the first, second and third (semi-)conductive regions and is arranged thereabove; and - a (semi-)conductive interconnection contact (17) which mutually connects said four (semi-)conductive regions (semi-)conductively, wherein at least two of the four (semi-)conductive regions extend substantially parallel to the substrate of the integrated circuit at a considerable lateral angle relative to each other.
摘要翻译：集成电路技术领域本发明涉及一种集成电路，包括： - 衬底，其具有布置在衬底中或衬底上的第一（半）导电区域; - 第二（半）导电区域，其相对于第一区域至少相当部分被隔离并且布置在第一区域的上方或附近; - 第三（半）导电区域，其相对于第一和第二（半）导电区域绝缘至少相当大的一部分，并且布置在其上方; - 第四（半）导电区域，其相对于第一，第二和第三（半）导电区域绝缘并且布置在其上方; 和（ - ）半导体区域（半导体）相互连接的（半）导电互连触点（17），其中所述四个（半）导电区域中的至少两个基本上平行于该集成电路相对于彼此具有相当大的横向角度。

4. 发明申请

WO2011048968A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO2011048968A1
公开(公告)日：2011-04-28
申请号：PCT/JP2010/067810
申请日：2010-10-05
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD. , YAMAZAKI, Shunpei , TSUBUKU, Masashi , NODA, Kosei , TOYOTAKA, Kouhei , WATANABE, Kazunori , HARADA, Hikaru
发明人： YAMAZAKI, Shunpei , TSUBUKU, Masashi , NODA, Kosei , TOYOTAKA, Kouhei , WATANABE, Kazunori , HARADA, Hikaru
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/8244 , H01L27/108 , H01L27/11 , H01L29/786
CPC分类号： H01L29/7869 , G06F15/76 , H01L27/10805 , H01L27/10873 , H01L27/11 , H01L27/1108 , H01L27/1112 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L28/60 , H01L29/24 , H01L29/41733 , H01L29/42384 , H01L29/78696
摘要： An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.
摘要翻译：目的是提供一种存储器件，其包括可通过具有低截止电流的薄膜晶体管无故障地操作的存储元件。提供了一种存储器件，其中包括至少一个包括氧化物半导体层的薄膜晶体管的存储元件被布置为矩阵。包括氧化物半导体层的薄膜晶体管具有高场效应迁移率和低截止电流，因此可以有利地操作而没有问题。此外，可以降低功耗。由于存储器件和像素可以形成在一个衬底上，所以这种存储器件在包括氧化物半导体层的薄膜晶体管被设置在显示器件的像素中的情况下是特别有效的。

5. 发明申请

WO1996029733A1 SELF-ALIGNED EDGE CONTROL IN SILICON ON INSULATOR 审中-公开
标题翻译：绝缘体硅中的自对准边缘控制
公开(公告)号：WO1996029733A1
公开(公告)日：1996-09-26
申请号：PCT/US1996003823
申请日：1996-03-21
申请人： PEREGRINE SEMICONDUCTOR CORP.
发明人： PEREGRINE SEMICONDUCTOR CORP. , BURGENER, Mark, L.
IPC分类号： H01L21/762
CPC分类号： H01L21/0242 , H01L21/02532 , H01L21/02694 , H01L21/76264 , H01L21/76281 , H01L27/1112 , H01L27/12 , H01L27/1203 , H01L28/20 , H01L29/78621 , H01L29/78654 , H01L29/78657
摘要： An improved process and structure for channel stop in silicon on insulator using LOCOS isolation are disclosed. Advantages include decreased ion dose requirements; reduced processing time; smaller DELTA W characteristics, thus, small transistor size and more precise process control over the edge of a MOSFET. the process also makes possible a wide range of transistor design capabilities and improved transistor operating parameters.
摘要翻译：公开了一种使用LOCOS隔离件在硅绝缘体上进行通道停止的改进方法和结构。优点包括降低离子剂量要求; 减少处理时间; 更小的DELTA W特性，因此，小晶体管尺寸和更精确的过程控制在MOSFET的边缘。该工艺还可以实现晶体管设计能力的广泛和晶体管工作参数的改进。

6. 发明申请

WO1996028849A1 CMOS CIRCUITRY WITH SHORTENED P-CHANNEL LENGTH ON ULTRATHIN SILICON ON INSULATOR 审中-公开
标题翻译： CMOS绝缘子上超薄硅胶P沟道长度的CMOS电路
公开(公告)号：WO1996028849A1
公开(公告)日：1996-09-19
申请号：PCT/US1996003022
申请日：1996-03-06
申请人： PEREGRINE SEMICONDUCTOR CORPORATION
发明人： PEREGRINE SEMICONDUCTOR CORPORATION , STAAB, David, R. , GREENE, Richard, M. , BURGENER, Mark, L. , REEDY, Ronald, E.
IPC分类号： H01L27/12
CPC分类号： H01L21/0242 , H01L21/02532 , H01L21/02694 , H01L21/76264 , H01L21/76281 , H01L21/86 , H01L27/1112 , H01L27/12 , H01L27/1203 , H01L28/20 , H01L29/78621 , H01L29/78654 , H01L29/78657
摘要： An integrated circuit comprising an insulating substrate; a layer of silicon formed on said insulating substrate; a p-channel transistor and an n-channel transistor formed in said silicon layer and interconnected in a CMOS circuit; wherein the ratio of transistor p-channel length to transistor n-channel length in the CMOS circuit is less than or equal to one.
摘要翻译：一种集成电路，包括绝缘基板; 形成在所述绝缘基板上的硅层; 形成在所述硅层中并在CMOS电路中互连的p沟道晶体管和n沟道晶体管; 其中CMOS电路中晶体管p沟道长度与晶体管n沟道长度的比值小于或等于1。

7. 发明申请

WO1989002655A1 INTEGRATED CIRCUIT TRENCH CELL 审中-公开
标题翻译：集成电路TRENCH CELL
公开(公告)号：WO1989002655A1
公开(公告)日：1989-03-23
申请号：PCT/US1988002723
申请日：1988-08-12
申请人： MOTOROLA, INC.
发明人： MOTOROLA, INC. , TENG, Ker-Wen , WANG, Karl, L. , NGUYEN, Bich-Yen , WU, Wei
IPC分类号： H01L29/78
CPC分类号： H01L27/0629 , H01L27/088 , H01L27/1104 , H01L27/1112 , H01L29/7827 , Y10S257/903
摘要： A multiple element integrated circuit trench cell (10) having at least one vertical field effect transistor (FET) (46) in a wall (17) of a trench (18) in a semiconductor substrate (12). The cell (10) further comprises a central load device (54) within the trench (18) which is electrically connected to the vertical FET (46). The central load device (54) may be an active load device, such as another field effect transistor, or a passive load device, such as a resistor. Additionally, a further FET (50) may be present in another wall (19) of the trench (18) or in a lateral orientation adjacent the trench (18) in the semiconductor surface (14). Two of these multiple element trench cells (10) may be interconnected in various configurations to form conventional static random access memory (SRAM) cells (56).

8. 发明申请

WO1984003587A1 INVERTED POLYCIDE SANDWICH STRUCTURE AND METHOD 审中-公开
标题翻译：反相聚合物三元结构和方法
公开(公告)号：WO1984003587A1
公开(公告)日：1984-09-13
申请号：PCT/US1984000366
申请日：1984-03-05
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , CHAN, Hugo, W., K.
IPC分类号： H01L21/74
CPC分类号： H01L29/4933 , H01L21/76801 , H01L21/76834 , H01L21/76889 , H01L23/53271 , H01L27/1112 , H01L28/20 , H01L2924/0002 , Y10S257/904 , H01L2924/00
摘要： A fabrication method and result integrated circuit structure that provide a second level of interconnect, a low resistance contact strap (10b) between underlying layers which is not sensitive to alignment and low lateral diffusion polysilicon load. The method comprises the steps of providing contact openings (45a, 45b, 45c) in an insulating layer (40) on a wafer (5) to any desired underlying circuit layers, depositing a silicide layer (50) on the wafer (5), removing selected portions of the silicide layer (50), depositing a polysilicon layer (55) on the wafer (5), lightly doping the polysilicon layer (55) to a level appropriate for the resistor (25), and then removing portions of the polysilicon (55) along with underlying silicide (50).

9. 发明申请

WO2003023847A2 INTEGRATED CIRCUIT, PORTABLE DEVICE AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路，便携式设备及制造集成电路的方法
公开(公告)号：WO2003023847A2
公开(公告)日：2003-03-20
申请号：PCT/IB2002/003628
申请日：2002-09-03
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： REINER, Joachim, C. , GRADENWITZ, Paul, G., M.
IPC分类号： H01L21/768
CPC分类号： H01L27/1112 , H01L21/76895 , H01L23/485 , H01L27/1108 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an integrated circuit, comprising: - a substrate with a first (semi-)conductive region arranged in or on the substrate; - a second (semi-)conductive region which is isolated for at least a considerable part relative to the first region and is arranged above or adjacent to the first region; - a third (semi-)conductive region which is insulated for at least a considerable part relative to the first and second (semi-)conductive regions and is arranged thereabove; - a fourth (semi-)conductive region which is insulated relative to the first, second and third (semi-)conductive regions and is arranged thereabove; and - a (semi-)conductive interconnection contact which mutually connects said four (semi-)conductive regions (semi-)conductively, wherein at least two of the four (semi-)conductive regions extend substantially parallel to the substrate of the integrated circuit at a considerable lateral angle relative to each other.
摘要翻译：集成电路技术领域本发明涉及一种集成电路，包括： - 衬底，其具有布置在衬底中或衬底上的第一（半）导电区域; - 第二（半）导电区域，其相对于第一区域至少相当部分被隔离并且布置在第一区域的上方或附近; - 第三（半）导电区域，其相对于第一和第二（半）导电区域绝缘至少相当大的一部分，并且布置在其上方; - 第四（半）导电区域，其相对于第一，第二和第三（半）导电区域绝缘并且布置在其上方; 以及 - 导电地互连所述四个（半）导电区域（半导体）的（半）导电互连触点，其中所述四个（半）导电区域中的至少两个基本上平行于所述集成电路的衬底延伸相对于彼此具有相当大的横向角度。

10. 发明申请

WO1997022148A1 SRAM CELL HAVING IMPROVED POLYSILICON RESISTOR STRUCTURES AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：具有改进的多晶硅电阻结构的SRAM单元及其形成方法
公开(公告)号：WO1997022148A1
公开(公告)日：1997-06-19
申请号：PCT/US1996014943
申请日：1996-09-18
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , CHANG, Kuang-Yeh , LIU, Yowjuang, W.
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L27/1112
摘要： A metal oxide semiconductor static random access memory (SRAM) includes NMOS transistors and resistor structures implemented without multiple polysilicon layers. According to a first embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors having transistor gates formed of a polysilicon layer and resistors formed of the same polysilicon layer. In accordance with a second embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors, a dielectric layer overlying the NMOS transistors, and polysilicon resistors passing through the dielectric layer to connect the NMOS transistors to a first metal layer. The dielectric layer, deposited on the NMOS transistors, defines holes exposing drain regions in the NMOS transistors. A polysilicon layer is deposited on the dielectric layer to fill the holes, and the excess polysilicon is removed.
摘要翻译：金属氧化物半导体静态随机存取存储器（SRAM）包括NMOS晶体管和不具有多个多晶硅层的电阻结构。根据第一实施例，SRAM单元包括多个适当互连的NMOS晶体管，其具有由多晶硅层形成的晶体管栅极和由相同多晶硅层形成的电阻器。根据第二实施例，SRAM单元包括多个适当互连的NMOS晶体管，覆盖NMOS晶体管的电介质层，以及穿过介电层的多晶硅电阻器，以将NMOS晶体管连接到第一金属层。沉积在NMOS晶体管上的电介质层限定了暴露在NMOS晶体管中的漏极区域的孔。在电介质层上沉积多晶硅层以填充孔，并且去除多余的多晶硅。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式