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1. 发明申请

WO1996025765A1 APPARATUS AND METHOD OF MAKING A SELF-ALIGNED INTEGRATED RESISTOR LOAD ON ULTRATHIN SILICON-ON-SAPPHIRE 审中-公开
标题翻译：在超薄硅胶上制备自对准的集成电阻负载的装置和方法
公开(公告)号：WO1996025765A1
公开(公告)日：1996-08-22
申请号：PCT/US1996001968
申请日：1996-02-09
申请人： PEREGRINE SEMICONDUCTOR CORPORATION
发明人： PEREGRINE SEMICONDUCTOR CORPORATION , REEDY, Ronald, E.
IPC分类号： H01L27/11
CPC分类号： H01L29/78657 , H01L21/0242 , H01L21/0245 , H01L21/02532 , H01L21/02694 , H01L27/1112 , H01L27/12 , H01L27/1203 , H01L28/20 , H01L29/78621 , H01L29/78654
摘要： A semiconductor on insulator composite substrate apparatus, such as silicon-on-sapphire and a method for fabricating the same. More particularly, a resistor, transistor, memory cell or other circuit element utilizing an ultrathin silicon layer on a sapphire substrate and a method for fabricating the same. An aspect of the invention provides a resistive load in the thin silicon layer which is self-aligned to a transistor or other circuit element, for example, enabling elimination of a polysilicon layer or enabling a compact memory cell, analog circuit or other integrated circuit. Another aspect of the invention is to eliminate or reduce parasitic effects. A third aspect of the invention is to improve process characteristics, and a fourth aspect of the invention is to improve production yields.
摘要翻译：一种绝缘体上半导体复合衬底装置，例如蓝宝石硅及其制造方法。更具体地，使用蓝宝石衬底上的超薄硅层的电阻器，晶体管，存储单元或其它电路元件及其制造方法。本发明的一个方面提供了薄硅层中的电阻负载，其与晶体管或其它电路元件自对准，例如，能够消除多晶硅层或实现紧凑的存储单元，模拟电路或其它集成电路。本发明的另一方面是消除或减少寄生效应。本发明的第三方面是改进工艺特性，本发明的第四方面是提高生产量。

2. 发明申请

WO1996022613A1 METHOD AND STRUCTURE FOR PROVIDING ESD PROTECTION FOR SILICON ON INSULATOR INTEGRATED CIRCUITS 审中-公开
标题翻译：绝缘子集成电路硅的ESD保护方法与结构
公开(公告)号：WO1996022613A1
公开(公告)日：1996-07-25
申请号：PCT/US1996000139
申请日：1996-01-04
申请人： PEREGRINE SEMICONDUCTOR CORPORATION
发明人： PEREGRINE SEMICONDUCTOR CORPORATION , STAAB, David, R. , LI, Sheau-Suey
IPC分类号： H01L27/02
CPC分类号： H01L27/0255
摘要： A method and structure for providing ESD protection for Silicon-On-Insulator (SOI) integrated circuits. The ESD protection circuit includes an electrically conductive pad and first conductor segment fabricated over an insulating layer. The first conductor segment connects the pad directly to a first node, without an intervening input resistor. A first diode is fabricated over the insulating layer and connected between the first node and a first voltage supply rail. Similarly, a second diode is fabricated over the insulating layer and connected between the first node and a second voltage supply rail. Ballast resistors can be included in series with each of the diodes. A cross power supply clamp, also fabricated over the insulating layer, is connected between the first and second voltage supply rails. The first node of the ESD protection circuit is coupled to the SOI integrated circuit to be protected. The ESD protection circuit can be fabricated on a minimum number of silicon islands to improve local thermal spreading. Improved ESD protection is provided to input, output, and I/O pins of an SOI integrated circuit, while promoting high speed signal transfer between these pins and the integrated circuit.
摘要翻译：一种用于为绝缘体上硅（SOI）集成电路提供ESD保护的方法和结构。 ESD保护电路包括导电焊盘和在绝缘层上制造的第一导体段。第一导体段将焊盘直接连接到第一节点，而没有中间输入电阻器。在绝缘层上制造第一二极管，并连接在第一节点和第一电压供应导轨之间。类似地，在绝缘层上制造第二二极管，并连接在第一节点和第二电压供应轨道之间。镇流电阻可以与每个二极管串联。也在绝缘层上制造的交叉电源钳被连接在第一和第二电压轨之间。 ESD保护电路的第一个节点耦合到要保护的SOI集成电路。 ESD保护电路可以制造在最小数量的硅岛上，以改善局部热扩散。提供了对SOI集成电路的输入，输出和I / O引脚的改进的ESD保护，同时促进了这些引脚和集成电路之间的高速信号传输。

3. 发明申请

WO1998016005A1 PHASE DETECTOR WITH EXPLICIT ASYNCHRONOUS RESET 审中-公开
标题翻译：相位检测器显示异步复位
公开(公告)号：WO1998016005A1
公开(公告)日：1998-04-16
申请号：PCT/US1997017173
申请日：1997-09-25
申请人： PEREGRINE SEMICONDUCTOR CORPORATION
发明人： PEREGRINE SEMICONDUCTOR CORPORATION , STAAB, David, R.
IPC分类号： H03D13/00
CPC分类号： H03D13/004
摘要： An embodiment of the present invention provides a phase detector (404) with an externally accessible initiallization (1L) node (408). In this embodiment, the phase detector includes a comparison circuit that compares a reference signal (FR) and a feedback signal (FV) to provide an output signal that represents at least one of the phase difference and the frequency difference between the reference signal and the feedback signal. In the present embodiment, the comparison circuit includes a memory element that it uses to provide the output signal. In particular, the memory element is a first flip-flop (202A) and a second flip-flop (202B). Accordingly, the output signal is the output of the first flip-flop and the output of the second flip-flop. The output signal is coupled to a reset circuit (402, 406). The reset circuit is fed back to a reset input (202A, 202B) of the comparison circuit to reset the comparison circuit in response to predetermined output signal. The externally accessible initiallization (1L) node is also coupled to the reset input of the comparison circuit to provide access to the reset input external to the phase detector. By providing this external access, the initiallization node facilitates logic simulation, testing and/or fault grading of circuits containing this phase detector embodiment.
摘要翻译：本发明的实施例提供一种具有外部可访问的初始化（1L）节点（408）的相位检测器（404）。在本实施例中，相位检测器包括比较电路，比较参考信号（FR）和反馈信号（FV）以提供输出信号，该输出信号表示参考信号和参考信号之间的相位差和频率差中的至少一个反馈信号。在本实施例中，比较电路包括用于提供输出信号的存储元件。特别地，存储元件是第一触发器（202A）和第二触发器（202B）。因此，输出信号是第一触发器的输出和第二触发器的输出。输出信号耦合到复位电路（402,406）。复位电路被反馈到比较电路的复位输入（202A，202B），以响应于预定的输出信号复位比较电路。外部可访问的初始化（1L）节点还耦合到比较电路的复位输入，以提供对相位检测器外部的复位输入的访问。通过提供这种外部访问，初始化节点便于包含该相位检测器实施例的电路的逻辑仿真，测试和/或故障分级。

4. 发明申请

WO1996026545A1 CAPACITOR ON ULTRATHIN SEMICONDUCTOR ON INSULATOR 审中-公开
标题翻译：绝缘子上绝缘半导体电容器
公开(公告)号：WO1996026545A1
公开(公告)日：1996-08-29
申请号：PCT/US1996002458
申请日：1996-02-20
申请人： PEREGRINE SEMICONDUCTOR CORPORATION
发明人： PEREGRINE SEMICONDUCTOR CORPORATION , BURGENER, Mark, L. , REEDY, Ronald, E. , SUNG, John, Y.
IPC分类号： H01L27/12
CPC分类号： H01L28/20 , H01L21/0242 , H01L21/02532 , H01L21/02694 , H01L27/12 , H01L29/94
摘要： An integrated circuit is provided which comprises: an insulating substrate; a semiconductor layer formed on the insulating substrate; a MOSFET including a source, drain and channel formed in the silicon layer and a gate adjacent to the channel; a gate terminal; and a conductor interconnecting the source and drain so as to maintain them at a common potential.
摘要翻译：提供一种集成电路，其包括：绝缘基板; 形成在所述绝缘基板上的半导体层; 包括在硅层中形成的源极，漏极和沟道的MOSFET和与沟道相邻的栅极; 门终端; 以及将源极和漏极互连以将它们保持在共同的电位的导体。

5. 发明申请

WO1995002892A1 HIGH-FREQUENCY WIRELESS COMMUNICATION SYSTEM ON A SINGLE ULTRATHIN SILICON ON SAPPHIRE CHIP 审中-公开
标题翻译：高效无线通信系统在SAPPHIRE芯片上的单层超细硅胶
公开(公告)号：WO1995002892A1
公开(公告)日：1995-01-26
申请号：PCT/US1994006626
申请日：1994-06-10
申请人： PEREGRINE SEMICONDUCTOR CORPORATION
发明人： PEREGRINE SEMICONDUCTOR CORPORATION , REEDY, Ronald, E. , BURGENER, Mark, L.
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01L21/0242 , H01L21/02532 , H01L21/02694 , H01L21/76264 , H01L21/76281 , H01L21/86 , H01L27/1112 , H01L27/12 , H01L27/1203 , H01L29/78621 , H01L29/78654 , H01L29/78657 , Y10S148/15 , Y10S438/967 , Y10S438/974 , Y10S438/977
摘要： A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.
摘要翻译：介绍了蓝宝石芯片上单个硅片上的高频无线通信系统。该系统在蓝宝石芯片上的单个超薄硅上集成了模拟，数字（逻辑和存储器）和高射频电路。器件采用常规体硅CMOS处理技术制造。优点包括单芯片架构，卓越的高频性能，低功耗和成本有效的制造。

6. 发明申请

WO1998023035A1 AN APPARATUS AND METHOD FOR REDUCING SPURIOUS SIDEBANDS IN PHASE LOCKED LOOPS 审中-公开
标题翻译：一种用于减少相位锁定鞋底中的刺激侧面的装置和方法
公开(公告)号：WO1998023035A1
公开(公告)日：1998-05-28
申请号：PCT/US1997020612
申请日：1997-11-12
申请人： PEREGRINE SEMICONDUCTOR CORPORATION
发明人： PEREGRINE SEMICONDUCTOR CORPORATION , DENNY, Paul, A.
IPC分类号： H03L07/093
CPC分类号： H03L7/095 , H03L7/0891 , H03L7/093 , Y10S331/02
摘要： An apparatus and method for reducing spurious sidebands in the tuning signal of phase locked loop frequency synthesizers and phase locked loops is disclosed. A frequency synthesizer comprises an oscillator, a divider, a difference circuit and a sampling circuit. The oscillator produces a variable frequency oscillator signal in response to an applied tuning signal. The divider circuit has a division factor and communicates with the oscillator to receive and divide the variable frequency oscillator signal by the division factor to produce a reduced frequency signal. The difference circuit communicates with the divider circuit to receive the reduced frequency signal and produce a difference signal. The difference signal corresponds to the phase difference between the reference signal and the reduced frequency signal. The sample circuit intermittently samples the difference signal in response to timing signal to produce a tuning signal which approaches a DC characteristic. The tuning signal serves to adjust the oscillator frequency in a direction to diminish phase differences in the reference signal and the reduced frequency signal. In another aspect of the invention, a PLL is disclosed with the sampling circuitry for intermittently sampling the difference signal in response to a timing signal.
摘要翻译：公开了一种用于减少锁相环频率合成器和锁相环调谐信号中的杂散边带的装置和方法。频率合成器包括振荡器，分频器，差分电路和采样电路。振荡器响应于所施加的调谐信号产生可变频率振荡器信号。分频电路具有分频因子并与振荡器通信，以便通过除频系数接收和分频可变频率振荡器信号以产生降频信号。差分电路与分频器电路进行通信，以接收降频信号并产生差分信号。差分信号对应于参考信号和降频信号之间的相位差。采样电路响应于定时信号间歇地采样差分信号，以产生接近直流特性的调谐信号。调谐信号用于调整振荡器频率的方向，以减小参考信号和降频信号的相位差。在本发明的另一方面，公开了一种具有采样电路的PLL，用于响应于定时信号间歇地采样差分信号。

7. 发明申请

WO1996028849A1 CMOS CIRCUITRY WITH SHORTENED P-CHANNEL LENGTH ON ULTRATHIN SILICON ON INSULATOR 审中-公开
标题翻译： CMOS绝缘子上超薄硅胶P沟道长度的CMOS电路
公开(公告)号：WO1996028849A1
公开(公告)日：1996-09-19
申请号：PCT/US1996003022
申请日：1996-03-06
申请人： PEREGRINE SEMICONDUCTOR CORPORATION
发明人： PEREGRINE SEMICONDUCTOR CORPORATION , STAAB, David, R. , GREENE, Richard, M. , BURGENER, Mark, L. , REEDY, Ronald, E.
IPC分类号： H01L27/12
CPC分类号： H01L21/0242 , H01L21/02532 , H01L21/02694 , H01L21/76264 , H01L21/76281 , H01L21/86 , H01L27/1112 , H01L27/12 , H01L27/1203 , H01L28/20 , H01L29/78621 , H01L29/78654 , H01L29/78657
摘要： An integrated circuit comprising an insulating substrate; a layer of silicon formed on said insulating substrate; a p-channel transistor and an n-channel transistor formed in said silicon layer and interconnected in a CMOS circuit; wherein the ratio of transistor p-channel length to transistor n-channel length in the CMOS circuit is less than or equal to one.
摘要翻译：一种集成电路，包括绝缘基板; 形成在所述绝缘基板上的硅层; 形成在所述硅层中并在CMOS电路中互连的p沟道晶体管和n沟道晶体管; 其中CMOS电路中晶体管p沟道长度与晶体管n沟道长度的比值小于或等于1。

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