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1. 发明申请

WO2014207825A1 プログラマブルコントローラ审中-公开
标题翻译：可编程控制器
公开(公告)号：WO2014207825A1
公开(公告)日：2014-12-31
申请号：PCT/JP2013/067403
申请日：2013-06-25
申请人：三菱電機株式会社
发明人：生山　知 , 山本　順司
IPC分类号： G05B19/05
CPC分类号： G06F13/362 , G05B19/05 , G06F13/4278
摘要：　実施の形態のプログラマブルコントローラは、データ送受信用のバスと、同期制御信号を伝達する同期制御信号線と、前記同期制御信号線に接続され、外部からの信号に基づいて前記同期制御信号を生成する同期制御信号生成ユニットと、前記バス及び前記同期制御信号線に接続され、前記同期制御信号に同期して外部機器からの信号を内部メモリにラッチするデータ保持ユニットと、前記バス及び前記同期制御信号線に接続され、前記同期制御信号に同期して前記バスを介して前記内部メモリの値を読み取るＣＰＵユニットと、を備える。
摘要翻译：根据实施例，该可编程控制器配备有：用于发送和接收数据的总线; 发送同步控制信号的同步控制信号线; 同步控制信号生成单元，其连接到所述同步控制信号线，并且基于外部信号生成所述同步控制信号; 数据保持单元，与所述总线和所述同步控制信号线连接，并且与所述同步控制信号同步地在内部存储器中锁存来自外部设备的信号; 以及连接到总线和同步控制信号线的CPU单元，并且与同步控制信号同步地经由总线读取内部存储器中的值。

2. 发明申请

WO2017099937A1 SINGLE-LINE PMIC-HOST LOW-LEVEL CONTROL INTERFACE 审中-公开
标题翻译：单线PMIC-HOST低电平控制接口
公开(公告)号：WO2017099937A1
公开(公告)日：2017-06-15
申请号：PCT/US2016/061392
申请日：2016-11-10
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan , CHUN, Chrisotpher Kong Yee , TAN, Chiew-Guan , LEE, Gordon , SUTTON, Todd
IPC分类号： G06F13/42
CPC分类号： H04L47/12 , G06F13/4278 , G06F13/4295 , H04L5/14 , H04L49/109 , H04W28/0221 , H04W52/0229 , Y02D70/122 , Y02D70/26
摘要： System, methods, and apparatus are described that facilitate signaling between devices over a single bi-directional line. In an example, the apparatus couples a first device to a second device via a single bi-directional line, indicates initiation of a first action, initiated at the first device, by sending a first single transition on the single bi-directional line from the first device to the second device, and indicates initiation of a second action, initiated at the second device, by sending a second single transition on the single bi-directional line from the second device to the first device. In another example, a first device initiates a first action, indicates initiation of the first action by generating a first event on a single bi-directional line, and receives an indication of a second action initiated at a second device by observing a second event on the single bi-directional line.
摘要翻译：描述了便于在单个双向线路上的设备之间的信令的系统，方法和设备。在一个示例中，该设备经由单个双向线路将第一设备耦合到第二设备，通过在单个双向线路上从第一设备发起的第一单动态转换指示在第一设备处发起的第一动作的发起并且指示在所述第二设备处发起的通过在所述单个双向线上从所述第二设备向所述第一设备发送第二单个转换的第二动作的发起。在另一示例中，第一设备发起第一动作，通过在单个双向线上生成第一事件来指示第一动作的发起，并且通过观察第二事件在第二设备处发起的第二动作的指示单一的双向线。

3. 发明申请

WO2016149212A1 ETHERNET AUTO-NEGOTIATION TECHNIQUES FOR DETERMINING LINK WIDTH 审中-公开
标题翻译：以太网自动调节技术用于确定链路宽度
公开(公告)号：WO2016149212A1
公开(公告)日：2016-09-22
申请号：PCT/US2016/022365
申请日：2016-03-14
申请人： INTEL CORPORATION
发明人： RAN, Adee O. , GANGA, Ilango S. , LUSTED, Kent C.
IPC分类号： H04L12/935 , H04L12/931 , H04L12/805
CPC分类号： H04L12/413 , G06F13/4278 , H04L12/40182
摘要： This disclosure describes, in one embodiment, a network node element that includes a multi-lane port that includes a plurality of lanes for communication with at least one link partner; PHY circuitry including transmit circuitry and receive circuitry for each lane of the multi-lane port; and an auto-negotiations circuitry to transmit, during an auto-negotiation period of transmission between the network controller and the at least one link partner, a first base page on a first lane of the multi-lane port to the link partner, the first base page including a field for specifying a transmit NONCE sequence number and a field for identifying at least one PHY capability and at least one link width associated with the PHY circuitry; the auto-negotiations circuitry also to receive, during the auto-negotiation period, a second base page on at least one lane from the at least one link partner, the second base page including a field for specifying a field for specifying an echoed NONCE sequence number and a field for identifying at least one PHY capability and at least one link width associated with the link partner; and wherein the auto-negotiations circuitry to determine if the link partner includes a multi-lane port or at least one single-lane port based on, at least in part, the at least one PHY capability identified in the second base page and to resolve a multi-lane connection or a single-lane connection with the link partner based on, at least in part, the at least one PHY capability identified in the second base page.
摘要翻译：本公开在一个实施例中描述了一种网络节点元素，其包括多通道端口，该多通道端口包括用于与至少一个链路伙伴进行通信的多个通道; PHY电路包括多通道端口的每个通道的发射电路和接收电路; 以及自动协商电路，用于在所述网络控制器与所述至少一个链路伙伴之间的传输自动协商期间将所述多通道端口的第一通道上的第一基页发送到所述链路伙伴，所述第一基本页面，其包括用于指定发送NONCE序列号的字段和用于识别至少一个PHY能力的字段和与所述PHY电路相关联的至少一个链路宽度; 所述自动协商电路还在所述自动协商周期期间接收来自所述至少一个链路伙伴的至少一个通道上的第二基页，所述第二基页包括用于指定用于指定回送的NONCE序列的字段的字段数字和字段，用于识别至少一个PHY能力和与所述链路伙伴关联的至少一个链路宽度; 并且其中所述自动协商电路基于至少部分地基于在所述第二基页中标识的所述至少一个PHY能力来确定所述链路伙伴是否包括多通道端口或至少一个单通道端口，并且解决至少部分地基于第二基页中标识的至少一个PHY能力，与链路伙伴的多通道连接或单通道连接。

4. 发明申请

WO2016058344A1 一种确定链路延时的方法、装置、通信设备和存储介质审中-公开
公开(公告)号：WO2016058344A1
公开(公告)日：2016-04-21
申请号：PCT/CN2015/076547
申请日：2015-04-14
申请人：深圳市中兴微电子技术有限公司
发明人：杨丽宁 , 郝鹏 , 黄灿
IPC分类号： G06F13/42
CPC分类号： G06F13/1689 , G06F11/3027 , G06F11/3419 , G06F13/1673 , G06F13/42 , G06F13/4278
摘要：本发明公开了一种确定链路延时的方法，该方法包括：依据预设的分频倍数对解析所得的每个数据通道的第一LMFC进行分频，得到对应每个数据通道的第二LMFC，并依据所述第二LMFC分别将所述每个数据通道中的数据写入相应缓存；依据SYSREF信号和预设的LMFC间隔产生第三LMFC，并依据所述第三LMFC分别将每个数据通道中的数据从相应缓存中读出；其中，所述第二LMFC的周期与所述第三LMFC的周期相同。本发明还同时公开了一种实现所述方法的装置、通信设备和存储介质。

5. 发明申请

WO2015120149A1 INCREASING THROUGHPUT ON MULTI-WIRE AND MULTI-LANE INTERFACES 审中-公开
标题翻译：在多线和多线接口上增加通路
公开(公告)号：WO2015120149A1
公开(公告)日：2015-08-13
申请号：PCT/US2015/014622
申请日：2015-02-05
申请人： QUALCOMM INCORPORATED
发明人： SENGOKU, Shoichiro
IPC分类号： G06F13/42
CPC分类号： G06F13/4068 , G06F1/08 , G06F13/4278
摘要： Systems, methods and apparatus extract data and clocks from a multi-wire bus that includes a first lane operated in accordance with a camera control interface (CCIe) mode of operation or a first lane operated in accordance with an N! mode of operation. Timing information derived from a sequence of symbols received from the first lane may be used to deserialize data received on a second lane of the multi-wire bus or decode a sequence of symbols received on the second lane. The symbols in a pair of consecutive symbols transmitted on the first lane cause different signaling states. Data on the second lane may be deserialized using on the receive clock derived from the timing information. In a CCIe lane, the final symbol of the sequence of symbols may be suppressed or a setup condition curtailed when the final symbol produces a signaling state equivalent to the setup condition.
摘要翻译：系统，方法和装置从多线总线提取数据和时钟，该多线总线包括根据照相机控制接口（CCIe）操作模式操作的第一通道，或者根据N＆操作模式。从从第一通道接收的符号序列导出的定时信息可用于对在多线总线的第二通道上接收的数据进行反序列化或解码在第二通道上接收的符号序列。在第一通道上发送的一对连续符号中的符号导致不同的信令状态。可以使用从定时信息导出的接收时钟对第二通道上的数据进行反序列化。在CCIe通道中，当最终符号产生与设置条件等效的信令状态时，符号序列的最终符号可被抑制或设置条件被限制。

6. 发明申请

WO2014074301A1 SELF TRACK SCHEME FOR MULTI FREQUENCY BAND SERIALIZER DE-SERIALIZER I/O CIRCUITS 审中-公开
标题翻译：多频段串行编解码器I / O电路的自拍方案
公开(公告)号：WO2014074301A1
公开(公告)日：2014-05-15
申请号：PCT/US2013/066194
申请日：2013-10-22
申请人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
发明人： LEE, Sheau Jiung , CHANG, Mau-Chung Frank , KIM, Yanghyo
IPC分类号： G06F13/00 , G06F13/38
CPC分类号： H04L27/38 , G06F5/16 , G06F13/4059 , G06F13/4072 , G06F13/4278 , H04L27/364
摘要： A serializer and de-serializer circuit having self tracking circuitry which is particularly well-suited for use in communicating digital data from one integrated circuit (chip) to another for implementing chip-to-chip communications is presented. The circuits are scalable and utilize a multi-frequency modulation mechanism (e.g., QAM) for converting digital data bits into a serial analog stream at multiple frequencies for communication over a chip I/O connection. The track pulse generated on the transmitter side is serialized through the same path as the data, and demodulated through the same path in the de-serializer to provide synchronization with the data, without the need for complicated base band processing.
摘要翻译：具有自我跟踪电路的串行器和解串器电路，其特别适用于将数字数据从一个集成电路（芯片）传送到另一个集成电路（芯片）以实现芯片到芯片通信。这些电路是可扩展的并且利用多频调制机制（例如，QAM），用于将数字数据位转换成多个频率的串行模拟流，用于通过芯片I / O连接进行通信。在发射机侧产生的跟踪脉冲通过与数据相同的路径进行串行化，并通过解串器中相同的路径解调，以提供与数据的同步，而不需要复杂的基带处理。

7. 发明申请

WO2009125260A1 MULTIRATE TRANSMISSION SYSTEM FOR PARALLEL INPUT DATA 审中-公开
标题翻译：用于并行输入数据的多路传输系统
公开(公告)号：WO2009125260A1
公开(公告)日：2009-10-15
申请号：PCT/IB2009/000393
申请日：2009-03-02
申请人： THINKLOGICAL INC. , REMLIN, Mark , ENGLER, Michael
发明人： REMLIN, Mark , ENGLER, Michael
IPC分类号： G06F13/42 , G06F13/40
CPC分类号： G06F13/4278 , G06F13/4045
摘要： A multirate transmission system for transmitting parallel input data from a first location to a second location includes a transmitter portion and a receiver portion. The transmitter portion receives the parallel data, including the information related to a parallel data clock and stores the data in a buffer where it is subsequently read and serialized for transmission on a serial data link to the receiver portion where it is deserialized, including recovery of the parallel data clock in the serialized data stream. The receiver portion stores the parallel data in a buffer where it is read at a data rate corresponding to the parallel data clock of the incoming parallel data. The parallel data at the transmitter portion is associated with generated control characters when parallel data is not read from the buffer associated with the transmitter portion.
摘要翻译：用于将并行输入数据从第一位置传输到第二位置的多速率传输系统包括发射机部分和接收机部分。发送器部分接收并行数据，包括与并行数据时钟有关的信息，并将数据存储在缓冲器中，随后读取和串行化数据，以便在被反序列化的接收器部分的串行数据链路上传输，包括恢复串行数据流中的并行数据时钟。接收器部分将并行数据存储在缓冲器中，在缓冲器中以与输入并行数据的并行数据时钟对应的数据速率读取数据。当从与发送器部分相关联的缓冲器未读取并行数据时，发送器部分处的并行数据与所生成的控制字符相关联。

8. 发明申请

WO2015160599A1 BIDIRECTIONAL TRANSMISSION OF USB DATA USING AUDIO/VIDEO DATA CHANNEL 审中-公开
标题翻译：使用音频/视频数据通道的USB数据的双向传输
公开(公告)号：WO2015160599A1
公开(公告)日：2015-10-22
申请号：PCT/US2015/024984
申请日：2015-04-08
申请人： LATTICE SEMICONDUCTOR CORPORATION
发明人： YI, Ju, Hwan , KIM, Young, II , AHN, Gijung , KIM, Min-Kyu , SHIM, Daeyun , KIM, Gyudong , CHOI, Hoon
IPC分类号： H04N21/436 , G06F13/38 , H04J3/02
CPC分类号： G06F13/4278 , G06F3/14 , G06F13/4068 , G09G5/006 , G09G2370/04 , G09G2370/047 , G09G2370/10
摘要： Embodiments relate to half-duplex bidirectional transmission of data compliant with a first standard (e.g., Universal Serial Bus (USB) standard) over a physical channel of a multimedia link for transmitting audio/video ("A/V") data compliant with a second standard (e.g., Mobile High-Definition Link (MHL) standard) between a source device and a sink device using time division multiplexing (TDM). The source device sends units of data including A/V data and forward data compliant with the first standard at first times whereas the sink device sends units of data including backward data compliant with the first standard at second times between transmissions from the source device. The first times do not overlap with the second times. Synchronization signals may be added to the first and second units of data to align character symbols embedded in the first and second units of data.
摘要翻译：实施例涉及通过多媒体链路的物理信道的符合第一标准（例如，通用串行总线（USB）标准）的数据的半双工双向传输，用于传输符合标准的音频/视频（“A / V”）数据使用时分复用（TDM）在源设备和宿设备之间的第二标准（例如，移动高清链路（MHL）标准）。源设备首次发送包括A / V数据的数据单元和符合第一标准的转发数据，而宿设备在来自源设备的传输之间的第二次发送包括与第一标准兼容的后向数据的数据单元。第一次不与第二次重叠。可以将同步信号添加到第一和第二数据单元以对准嵌入在第一和第二数据单元中的字符符号。

9. 发明申请

WO2015134071A1 CLOCK RECOVERY CIRCUIT FOR MULTIPLE WIRE DATA SIGNALS 审中-公开
标题翻译：多路数据信号的时钟恢复电路
公开(公告)号：WO2015134071A1
公开(公告)日：2015-09-11
申请号：PCT/US2014/065169
申请日：2014-11-12
申请人： QUALCOMM INCORPORATED
发明人： SENGOKU, Shoichiro , WILEY, George Alan , LEE, Chulkyu
IPC分类号： H04L7/033 , H03K5/1252 , H03K5/1534 , H04L25/49 , H04L25/14
CPC分类号： H04L7/033 , G06F13/40 , G06F13/4278 , H04L25/0292
摘要： A plurality of line interfaces is configured to receive a spread signal over the plurality of line interface. The spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols. The spread signal is defined by a plurality of transition signals including a first signal over a first line interface. A clock signal is extracted based on a comparison between a first instance of the first signal and a delayed second instance of the first signal. The delayed second instance of the first signal is sampled based on the clock signal to provide a symbol output. The clock extraction circuit is further adapted to generate the clock signal based on additional comparisons between a first instance of a second signal, within the plurality of transition signals, and a delayed second instance of the second signal, where the first and second signals are concurrent signals received over different line interfaces.
摘要翻译：多个线路接口被配置为在多个线路接口上接收扩展信号。扩展信号携带符号，其中连续符号之间保证符号到符号状态转换。扩展信号由包括第一线路接口上的第一信号的多个转换信号定义。基于第一信号的第一实例和第一信号的延迟的第二实例之间的比较来提取时钟信号。基于时钟信号对第一信号的延迟第二实例进行采样以提供符号输出。时钟提取电路还适于基于多个转换信号之间的第二信号的第一实例与第二信号的延迟的第二实例之间的附加比较来生成时钟信号，其中第一和第二信号是并发的通过不同线路接口接收的信号。

10. 发明申请

WO2015021257A1 N-PHASE SIGNAL TRANSITION ALIGNMENT 审中-公开
标题翻译： N相信号转换对准
公开(公告)号：WO2015021257A1
公开(公告)日：2015-02-12
申请号：PCT/US2014/050108
申请日：2014-08-07
申请人： QUALCOMM INCORPORATED
发明人： LEE, Chulkyu , WILEY, George Alan
IPC分类号： G06F13/42 , H04L25/49
CPC分类号： G06F13/36 , G06F13/4063 , G06F13/4068 , G06F13/4278 , G06F13/4282 , H04L7/0033 , H04L25/14 , H04L25/4917 , H04L25/4919 , Y02D10/14 , Y02D10/151
摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Drivers may be adapted or configured to align state transitions on two or more connectors in order to minimize a transition period between consecutive symbols. The drivers may include circuits that advance or delay certain transitions. The drivers may include pre-emphasis circuits that operate to drive the state of a connector for a portion of the transition period, even when the connector is transitioned to an undriven state.
摘要翻译：描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。信息以N相极性编码符号发送。驱动器可以被适配或配置成在两个或更多个连接器上对准状态转换，以使连续符号之间的过渡周期最小化。驱动器可以包括推进或延迟某些转换的电路。驱动器可以包括预加重电路，即，即使当连接器转换到未驱动状态时，该预加重电路用于驱动连接器的一部分过渡期的状态。

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