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1. 发明申请

WO2004102403A3 A SYSTEM INCLUDING A HOST CONNECTED TO A PLURALITY OF MEMORY MODULES VIA A SERIAL MEMORY INTERCONNECT 审中-公开
标题翻译：包括通过串行存储器互连连接到多个存储器模块的主机的系统
公开(公告)号：WO2004102403A3
公开(公告)日：2005-08-25
申请号：PCT/US2004014441
申请日：2004-05-10
申请人： ADVANCED MICRO DEVICES INC , POLZIN R STEPHEN , WEBER FREDERICK D , TALBOT GERALD R , HEWITT LARRY D , REEVES RICHARD W , PATEL SHWETAL A , LA FETRA ROSS V , GULICK DALE E , HUMMEL MARK D , MIRANDA PAUL C
发明人： POLZIN R STEPHEN , WEBER FREDERICK D , TALBOT GERALD R , HEWITT LARRY D , REEVES RICHARD W , PATEL SHWETAL A , LA FETRA ROSS V , GULICK DALE E , HUMMEL MARK D , MIRANDA PAUL C
IPC分类号： G06F12/00 , G06F13/16 , G06F13/28 , G11C5/00 , G06F13/42
CPC分类号： G06F13/4243 , G06F12/0215 , G06F12/0862 , G06F13/1626 , G06F2212/6022
摘要： A system (50) including a host (100) coupled to a serially connected chain of memory modules (150A-B). In one embodiment, each of the memory modules includes a memory control hub (160) for controlling access to a plurality of memory chips (261) on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links (110). Each memory link may include an uplink (211) for conveying transactions toward the host and a downlink (212) for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.
摘要翻译：一种系统（50），包括耦合到串行连接的存储器模块链（150A-B）的主机（100）。在一个实施例中，每个存储器模块包括用于控制对存储器模块上的多个存储器芯片（261）的访问的存储器控制集线器（160）。存储器模块通过多个存储器链路（110）以链式串行耦合到主机。每个存储器链路可以包括用于向主机传送事务的上行链路（211）和用于将在主机处发起的事务传送到链路中的下一个存储器模块的下行链路（212）。上行链路和下行链路可以使用包括控制和配置分组和存储器访问分组的分组来传送事务。存储器控制集线器可以在第二存储器链路的第二下行链路上传送在第一存储器链路的第一下行链路上接收的事务，而与解码事务无关。

2. 发明申请

WO0159565A2 COMPUTER SYSTEM INCLUDING A MEMORY ACCESS CONTROLLER FOR USING NON-SYSTEM MEMORY STORAGE RESOURCES DURING SYSTEM BOOT TIME 审中-公开
标题翻译：包括在系统引导时间内使用非系统存储资源的存储器访问控制器的计算机系统
公开(公告)号：WO0159565A2
公开(公告)日：2001-08-16
申请号：PCT/US0100076
申请日：2001-01-02
申请人： ADVANCED MICRO DEVICES INC
发明人： GULICK DALE E
IPC分类号： G06F12/08 , G06F9/445 , G06F12/00
CPC分类号： G06F9/4401
摘要： A computer system including a memory access controller for using non-system memory storage resources during system boot time. A computer system includes a microprocessor, a system memory and a plurality of peripheral devices coupled to the microprocessor through one or more buses. A system controller and a peripheral bus controller control the buses. Many peripheral device controllers contain buffer memory used during normal system operation, by the peripheral device controllers, to buffer data between the computer system and the peripheral devices. The computer system also includes a memory access controller and a configuration storage unit. The configuration storage unit stores configuration control information which causes control logic to configure the buffer memory. The memory access controller controls accesses to the buffer memory associated with the peripheral devices during system initialization to allow use of the buffer memory as a stack or scratchpad RAM.
摘要翻译：一种计算机系统，包括在系统引导期间使用非系统存储器存储资源的存储器访问控制器。计算机系统包括微处理器，系统存储器和通过一个或多个总线耦合到微处理器的多个外围设备。系统控制器和外围总线控制器控制总线。许多外围设备控制器包含在正常系统操作期间由外围设备控制器在计算机系统和外围设备之间缓冲数据的缓冲存储器。计算机系统还包括存储器访问控制器和配置存储单元。配置存储单元存储使控制逻辑配置缓冲存储器的配置控制信息。存储器访问控制器在系统初始化期间控制与外围设备相关联的缓冲存储器的访问，以允许将缓冲存储器用作堆栈或暂存器RAM。

3. 发明申请

WO03038646A2 MICROCOMPUTER BRIDGE ARCHITECTURE WITH AN EMBEDDED MICROCONTROLLER 审中-公开
标题翻译：具有嵌入式微控制器的微型计算机桥接架构
公开(公告)号：WO03038646A2
公开(公告)日：2003-05-08
申请号：PCT/US0228980
申请日：2002-09-12
申请人： ADVANCED MICRO DEVICES INC
发明人： GULICK DALE E
IPC分类号： G06F13/36 , G06F13/00 , G06F13/38 , G06F13/40 , G06F15/78 , H04L12/24 , H04L12/413
CPC分类号： H04L41/00 , G06F13/387
摘要： An integrated circuit, a computer system, and a method of operating the computer system. The integrated circuit includes an internal bus and a microcontroller connected to the internal bus. The microcontroller is configured to master the internal bus. An Ethernet controller may also be coupled to the internal bus with a plurality of buffers coupled between the microcontroller and the Ethernet controller for buffering data between the microcontroller and the Ethernet controller. The Ethernet controller and the microcontroller are then configured to exchange data over the internal bus.
摘要翻译：集成电路，计算机系统和操作计算机系统的方法。集成电路包括内部总线和连接到内部总线的微控制器。微控制器配置为掌握内部总线。以太网控制器还可以与耦合在微控制器和以太网控制器之间的多个缓冲器耦合到内部总线，用于缓冲微控制器和以太网控制器之间的数据。然后将以太网控制器和微控制器配置为通过内部总线交换数据。

4. 发明申请

WO2004003757A3 DIRECT TRANSACTION MODE FOR PERIPHERAL DEVICES 审中-公开
标题翻译：外围设备的直接交易模式
公开(公告)号：WO2004003757A3
公开(公告)日：2004-05-21
申请号：PCT/US0320807
申请日：2003-06-24
申请人： ADVANCED MICRO DEVICES INC
发明人： GULICK DALE E
IPC分类号： G06F13/40 , G06F13/12
CPC分类号： G06F13/4059
摘要： A method and system for more directly reading from or writing to a peripheral device (8) coupled to a computer via a standard communication protocol (such as Universal Serial Bus (USB)) by bypassing portions of the standard communication technology. The host controller (4) monitors the status of a direct command queue (52) afterthe completion of each standard communication transaction. If a command is present in the direct command queue, the command is carried out before any standard communication transactions are performed. If no command is present in the direct command queue, a standard communication transaction is carried out. The relatively long latency encountered when accessing critical command and status registers via standard communication technology is thus avoided.
摘要翻译：本发明提供了一种方法和系统，用于通过绕过标准通信技术的部分而更直接地从经由标准通信协议（诸如通用串行总线（USB））耦合到计算机的外围设备（8）读取或向其写入。主控制器（4）在完成每个标准通信事务之后监视直接命令队列（52）的状态。如果在直接命令队列中存在命令，则在执行任何标准通信事务之前执行该命令。如果在直接命令队列中不存在命令，则执行标准通信事务。因此避免了通过标准通信技术访问关键命令和状态寄存器时遇到的相对较长的延迟。

5. 发明申请

WO0219078A2 SYSTEM AND METHOD FOR MONITORING AND CONTROLLING A POWER MANAGEABLE RESOURCE 审中-公开
标题翻译：用于监控和控制电力可管理资源的系统和方法
公开(公告)号：WO0219078A2
公开(公告)日：2002-03-07
申请号：PCT/US0115122
申请日：2001-05-09
申请人： ADVANCED MICRO DEVICES INC
发明人： GULICK DALE E
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3215
摘要： A system and method for monitoring and controlling a power-manageable resource (16). In one embodiment, a power manageable resource, such as a bus in a computer system, may be shareable among a number of power-manageable devices (21A-21C). A resource monitor (25) may also be coupled to the power-manageable resource. The resource monitor may be configured to monitor the devices coupled to the power manageable resource. More specifically, the functions of the resource monitor may include monitoring the active/inactive state of each of the attached devices. The resource monitor may be configured to cause the sharable resource to be powered down if it is determined that all the attached devices are in an inactive state.
摘要翻译：一种用于监视和控制可管理资源的系统和方法（16）。在一个实施例中，诸如计算机系统中的总线的电力可管理资源可以在多个功率可管理装置（21A-21C）之间共享。资源监视器（25）还可以耦合到功率可管理的资源。资源监视器可以被配置为监视耦合到电力可管理资源的设备。更具体地，资源监视器的功能可以包括监视每个附加设备的主动/不活动状态。如果确定所有连接的设备处于非活动状态，则资源监视器可以被配置为使可共享资源被断电。

6. 发明申请

WO9615484A3 MONOLITHIC PC AUDIO CIRCUIT MONOLITHIC PC AUDIO CIRCUIT 审中-公开
标题翻译：单声道PC音频电路单声道PC音频电路
公开(公告)号：WO9615484A3
公开(公告)日：1997-02-06
申请号：PCT/US9514254
申请日：1995-11-02
申请人： ADVANCED MICRO DEVICES INC
发明人： HEWITT LARRY D , BLUMENTHAL JEFFREY M , BREHMER GEOFFREY E , BROWN GLEN W , CABLER CARLIN DRU , FEEMSTER RYAN , GUERCIO DAVID , GULICK DALE E , HOGAN MICHAEL , LINZ ALFREDO R , NORRIS DAVID , SCHNIZLEIN PAUL G , SOQUES MARTIN P , SPAK MICHAEL E , SUGGS DAVID N , TOROK ALAN T
IPC分类号： F02B75/02 , G06F3/16 , G10H1/00 , G10H1/12 , G10H7/00 , G10H7/02 , H03K23/68 , H03M1/66 , H03M3/02 , H03M7/32 , G06F
CPC分类号： H03K23/68 , F02B2075/027 , G06F3/162 , G10H1/0066 , G10H1/125 , G10H7/002 , G10H2220/315 , G10H2230/035 , G10H2240/311 , G10H2250/115 , G10H2250/191 , G10H2250/545 , G10H2250/571 , G10H2250/605 , G10H2250/611
摘要： A monolithic integrated circuit for providing enhanced audio performance in personal computers is disclosed. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit (CODEC) including analog-to-digital and digital-to-analog data conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

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