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1. 发明申请

WO2004102403A3 A SYSTEM INCLUDING A HOST CONNECTED TO A PLURALITY OF MEMORY MODULES VIA A SERIAL MEMORY INTERCONNECT 审中-公开
标题翻译：包括通过串行存储器互连连接到多个存储器模块的主机的系统
公开(公告)号：WO2004102403A3
公开(公告)日：2005-08-25
申请号：PCT/US2004014441
申请日：2004-05-10
申请人： ADVANCED MICRO DEVICES INC , POLZIN R STEPHEN , WEBER FREDERICK D , TALBOT GERALD R , HEWITT LARRY D , REEVES RICHARD W , PATEL SHWETAL A , LA FETRA ROSS V , GULICK DALE E , HUMMEL MARK D , MIRANDA PAUL C
发明人： POLZIN R STEPHEN , WEBER FREDERICK D , TALBOT GERALD R , HEWITT LARRY D , REEVES RICHARD W , PATEL SHWETAL A , LA FETRA ROSS V , GULICK DALE E , HUMMEL MARK D , MIRANDA PAUL C
IPC分类号： G06F12/00 , G06F13/16 , G06F13/28 , G11C5/00 , G06F13/42
CPC分类号： G06F13/4243 , G06F12/0215 , G06F12/0862 , G06F13/1626 , G06F2212/6022
摘要： A system (50) including a host (100) coupled to a serially connected chain of memory modules (150A-B). In one embodiment, each of the memory modules includes a memory control hub (160) for controlling access to a plurality of memory chips (261) on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links (110). Each memory link may include an uplink (211) for conveying transactions toward the host and a downlink (212) for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.
摘要翻译：一种系统（50），包括耦合到串行连接的存储器模块链（150A-B）的主机（100）。在一个实施例中，每个存储器模块包括用于控制对存储器模块上的多个存储器芯片（261）的访问的存储器控制集线器（160）。存储器模块通过多个存储器链路（110）以链式串行耦合到主机。每个存储器链路可以包括用于向主机传送事务的上行链路（211）和用于将在主机处发起的事务传送到链路中的下一个存储器模块的下行链路（212）。上行链路和下行链路可以使用包括控制和配置分组和存储器访问分组的分组来传送事务。存储器控制集线器可以在第二存储器链路的第二下行链路上传送在第一存储器链路的第一下行链路上接收的事务，而与解码事务无关。

2. 发明申请

WO9923548A3 MULTIFUNCTION FLOATING POINT ADDITION/SUBTRACTION PIPELINE AND BIPARTITE LOOK-UP TABLE 审中-公开
标题翻译：多功能浮点加法/减法管道和双比特查找表
公开(公告)号：WO9923548A3
公开(公告)日：1999-08-05
申请号：PCT/US9822453
申请日：1998-10-22
申请人： ADVANCED MICRO DEVICES INC
发明人： OBERMAN STUART F , JUFFA NORBERT , ROBERTS MARK E , WEBER FREDERICK D , CHERUKURI RAVI KRISHNA , RAMANI KRISHNAN
IPC分类号： G06F7/50 , G06F7/57 , G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38 , G06F17/16 , H03M7/24 , G06F1/035 , G06F7/00
CPC分类号： H03M7/24 , G06F7/483 , G06F7/509 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/3017 , G06F9/3804 , G06F9/3885 , G06F17/16
摘要： An add/subtract pipeline has far and close data paths. The far data path handles effective addition operations, and effective subtraction operations for operands having an absolute exponent difference greater than one. The close data path handles all other effective subtraction operations. Selection of the output value in the close data path effectuates the round-to-nearest operation. Floating point-to-integer conversion may be executed in the far data path integer-to-floating point instructions in the close data path. The execution unit may include a pluraliy of add/subtract pipelines, allowing vectored add, subtract, and integer/floating point conversion instructions to be performed. Additional arithmetic instructions (such as reverse subtract and accumulate functions minimum/maximum and comparison) may also be implemented. A method for generating entries for a bipartite look-up table having base and difference table portions is also disclosed. So is a multi-function look-up table.
摘要翻译：加/减管道具有远近数据路径。远数据路径处理有效加法运算，并对绝对指数差大于1的操作数进行有效减法运算。关闭数据路径处理所有其他有效的减法操作。关闭数据路径中的输出值的选择将实现轮到最近的操作。可以在关闭数据路径中的远端数据路径中的整数到浮点指令中执行浮点到整数的转换。执行单元可以包括多个加/减管道，允许执行矢量加，减和整数/浮点转换指令。额外的算术指令（如反向减法和累加函数最小/最大值和比较）也可以实现。还公开了一种用于为具有基表和差表部分的二分查找表生成条目的方法。所以是一个多功能查找表。

3. 发明申请

WO2004029812A2 COMPUTER SYSTEM WITH PROCESSOR CACHE THAT STORES REMOTE CACHE PRESENCE INFORMATION 审中-公开
标题翻译：具有处理器缓存的计算机系统存储远程缓存存在信息
公开(公告)号：WO2004029812A2
公开(公告)日：2004-04-08
申请号：PCT/US0331020
申请日：2003-09-18
申请人： ADVANCED MICRO DEVICES INC
发明人： CONWAY PATRICK , WEBER FREDERICK D
IPC分类号： G06F12/08
CPC分类号： G06F12/082 , G06F2212/2515 , Y02D10/13
摘要： A computer system with a processor cache that stores remote cache presence information. In one embodiment, a plurality of presence vectors are stored to indicate whether particular blocks of data mapped to another node are being remotely cached. Rather than storing the presence vectors in a dedicated storage, the remote cache presence vectors may be stored in designated locations of a cache memory subsystem (52), such as an L2 cache, associated with a processor core (50). For example, a designated way of the cache memory subsystem may be allocated for storing remote cache presence vectors, while the remaining ways of the cache are used to store normal processor data. New data blocks may be remotely cached in response to evictions from the cache memory subsystem. In yet a further embodiment, additional entries of the cache memory subsystem may be used for storing directory entries to filter probe command and response traffic.
摘要翻译：具有存储远程缓存存在信息的处理器高速缓存的计算机系统。在一个实施例中，存储多个存在向量以指示映射到另一节点的特定数据块是否被远程高速缓存。而不是将存在向量存储在专用存储器中，远程高速缓存存在向量可以存储在与处理器核心（50）相关联的高速缓存存储器子系统（52）（诸如L2高速缓存）的指定位置。例如，缓存存储器子系统的指定方式可被分配用于存储远程高速缓存存在向量，而高速缓存的剩余方式用于存储正常的处理器数据。响应于来自高速缓冲存储器子系统的驱逐，可以远程高速缓存新的数据块。在又一个实施例中，高速缓冲存储器子系统的附加条目可以用于存储目录条目以过滤探测命令和响应业务。

4. 发明申请

WO9921078A3 A METHOD AND APPARATUS FOR MULTI-FUNCTION ARITHMETIC 审中-公开
标题翻译：一种用于多功能算术的方法和装置
公开(公告)号：WO9921078A3
公开(公告)日：1999-08-12
申请号：PCT/US9822346
申请日：1998-10-22
申请人： ADVANCED MICRO DEVICES INC
发明人： OBERMAN STUART F , JUFFA NORBERT , SIU MING , WEBER FREDERICK D , CHERUKURI RAVI KRISHNA
IPC分类号： G06F7/50 , G06F7/52 , G06F7/533 , G06F7/544 , G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38 , G06F17/16 , H03M7/24 , G06F7/552
CPC分类号： G06F7/53 , G06F7/4991 , G06F7/49936 , G06F7/49963 , G06F7/49994 , G06F7/509 , G06F7/5338 , G06F7/5443 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/3017 , G06F9/3804 , G06F9/3885 , G06F17/16 , G06F2207/3828 , H03M7/24
摘要： A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines. The segments may be rounded by adding a rounding constant. Rounding and normalization may be performed in two paths, one assuming an overflow will occur, the other assuming no overflow will occur. The multiplier may also be configured to perform iterative calculations to evalutate constant powers of an operand. Intermediate products that are formed may be rounded and normalized in two paths and then compressed and stored for use in the next iteration. An adjustment constant may also be added to increase the frequency of exactly rounded results.
摘要翻译：公开了能够执行有符号和无符号标量和矢量乘法的乘法器。当执行向量乘法时，乘法器可以被配置为产生和选择部分乘积，以便有效地隔离每对向量分量的乘法过程。乘法器还可以被配置为对矢量分量的乘积求和以形成向量点积。最终产品可以分段输出，以便需要更少的总线。可以通过添加舍入常数来对段进行舍入。可以在两个路径中执行舍入和归一化，一个假设将发生溢出，另一个假设不会发生溢出。乘法器还可以被配置为执行迭代计算以评估操作数的恒定功率。形成的中间产品可以在两个路径中进行圆化和归一化，然后压缩并存储以用于下一次迭代。还可以添加调整常数以增加精确舍入结果的频率。

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