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1. 发明申请

WO2006083555A3 DIGITALLY PROGRAMMABLE DELAY CIRCUIT WITH PROCESS POINT TRACKING 审中-公开
标题翻译：具有过程点跟踪的数字可编程延迟电路
公开(公告)号：WO2006083555A3
公开(公告)日：2006-11-23
申请号：PCT/US2006001727
申请日：2006-01-19
申请人： TIMELAB CORP , CARLEY ADAM L , ALLEN DANIEL J , MANDRY JAMES E
发明人： CARLEY ADAM L , ALLEN DANIEL J , MANDRY JAMES E
IPC分类号： H03K17/296
CPC分类号： H03K5/133 , H03K2005/00065 , H03K2005/00221
摘要： A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed.
摘要翻译：一种数字可编程延迟电路，包括彼此并联连接的多个晶体管以及承载具有待延迟边缘的信号的线。

2. 发明申请

WO2006083556A3 DELAY CIRCUIT FOR SYNCHRONIZING ARRIVAL OF A CLOCK SIGNAL AT DIFFERENT CIRCUIT BOARD POINTS 审中-公开
标题翻译：用于同步不同电路板时钟信号的延迟电路
公开(公告)号：WO2006083556A3
公开(公告)日：2007-01-04
申请号：PCT/US2006001728
申请日：2006-01-19
申请人： TIMELAB CORP , CARLEY ADAM L , ALLEN DANIEL J , MANDRY JAMES E
发明人： CARLEY ADAM L , ALLEN DANIEL J , MANDRY JAMES E
IPC分类号： G06F1/04
CPC分类号： H03H11/265
摘要： A clock signal generation system and method to distribute at least one clock signal to a plurality of points on a circuit board using a plurality of digitally programmable delay circuits (10) each of which delays the clock signal (Clockln) by a desired amount so as to synchronize arrival of the clock signal when distributed to each of the plurality of points on the circuit. Each digitally programmable delay circuits (10) comprises a plurality of circuit stages (100(l)-100(N)) connected in series with each other. Each circuit stage comprises a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other, and a plurality of transistors of a second type (c.g., N-type) connected in parallel with each other in each circuit stage, one or more of the plurality of transistors of the first type are selected to delay a rising edge, and one or more of the plurality of transistors of a second type are selected to delay a falling edge.
摘要翻译：一种时钟信号产生系统和方法，用于使用多个数字可编程延迟电路（10）将至少一个时钟信号分配到电路板上的多个点，每个延迟电路将时钟信号（Clock1n）延迟期望的量，以便当分配给电路上的多个点中的每个点时，同步时钟信号的到达。每个数字可编程延迟电路（10）包括彼此串联连接的多个电路级（100（1）-100（N））。每个电路级包括彼此并联连接的多个第一类型的晶体管（例如，P型），以及在每个电路平台中彼此并联连接的第二类型（cg，N型）的多个晶体管选择第一类型的多个晶体管中的一个或多个以延迟上升沿，并且选择第二类型的多个晶体管中的一个或多个延迟下降沿。

3. 发明申请

WO2006044586A3 SPREAD SPECTRUM CLOCK SIGNAL GENERATION SYSTEM AND METHOD 审中-公开
标题翻译：传播频谱信号发生系统和方法
公开(公告)号：WO2006044586A3
公开(公告)日：2007-02-01
申请号：PCT/US2005036918
申请日：2005-10-12
申请人： TIMELAB CORP , CARLEY ADAM L , ALLEN DANIEL J
发明人： CARLEY ADAM L , ALLEN DANIEL J
IPC分类号： H04B1/69
CPC分类号： G06F1/08
摘要： A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal. The programmable modulator is coupled to an arbitrary waveform synthesizer that generates timing for edges of the clock signal based on the edge position values. A variety of modulations can be imposed on the clock signal using these techniques, including triangle wave modulation, near-triangle modulation, random and pseudo-random modulation.
摘要翻译：一种用于产生具有扩频调制的时钟信号的系统和方法。该方法涉及通过从针对每个边缘的定时的数字表示产生时钟信号的边缘的边缘位置来产生时钟信号，以将扩频调制传递给时钟信号。提供了一种可编程调制器，其基于时变周期值和时变占空比值中的至少一个，生成表示时钟信号的边沿的边缘位置的数字值。可编程调制器可以包括产生时变数字周期值的称为周期调制电路的第一电路和产生时变数字占空比值的称为占空比调制电路的第二电路。处理时变周期值和时变占空比值以产生指定时钟信号的边沿位置的数字边沿位置值。可编程调制器耦合到任意波形合成器，其基于边缘位置值产生时钟信号的边沿的定时。使用这些技术可以对时钟信号施加各种调制，包括三角波调制，近三角调制，随机和伪随机调制。

4. 发明申请

WO2005077034A2 HIGH SPEED SERIALIZER-DESERIALIZER 审中-公开
标题翻译：高速串联器 - DESERIALIZER
公开(公告)号：WO2005077034A2
公开(公告)日：2005-08-25
申请号：PCT/US2005003992
申请日：2005-02-09
申请人： TIMELAB CORP , CARLEY ADAM L
发明人： CARLEY ADAM L
IPC分类号： H03M5/08 , H03M7/00
CPC分类号： H03M5/08
摘要： A high speed serializer-deserializer (SerDes) that passes significantly more data through a channel for a given analog bandwidth and signal-to-noise ratio. This SerDes technique involves converting a plurality of bits to be transferred to positions of edges of a waveform that is transmitted over at least one transmission wire from a source to a destination. The plurality of bits are converted to edges in order to position edges such that more than k inter-edge spacings are possible over a range of spacings between T and kT, where k is a real number greater than 1 and T is the minimum spacing between consecutive edges. An edge position translation scheme that maps patterns in a stream of input bits to a corresponding spacing between a rising edge and a falling edge of the waveform, or between a falling edge and a rising edge of the waveform. The bits are recovered at the destination by detecting the edges in the received waveform at the destination and driving a stream of binary numbers representing time intervals between detected consecutive edges (inter-edge spacings). The stream of binary numbers is decoded according to the edge position translation scheme to recover corresponding bits.
摘要翻译：一种高速串行器 - 解串器（SerDes），通过通道显示更多的数据，以获得给定的模拟带宽和信噪比。该SerDes技术涉及将要传送的多个比特转换到通过至少一根传输线从源传输到目的地的波形边缘的位置。将多个位转换为边缘以便定位边缘，使得在T和kT之间的间隔范围内多于k个边缘间隔是可能的，其中k是大于1的实数，T是大于1的实数，并且T是连续边缘边缘位置转换方案，将输入比特流中的图形映射到波形的上升沿和下降沿之间的相应间隔，或波形的下降沿和上升沿之间。通过检测目的地的接收波形中的边缘，并且驱动表示检测到的连续边缘之间的时间间隔（边缘间隔）的二进制数据流，在目的地恢复比特。根据边缘位置转换方案对二进制数字流进行解码，以恢复相应的位。

5. 发明申请

WO2004015743A3 CLOCK DISTRIBUTOR CIRCUIT FOR MAINTAINING A PHASE RELATIONSHIP BETWEEN REMOTE OPERATING NODES AND A REFERENCE CLOCK ON A CHIP 审中-公开
标题翻译：用于维持远程操作数和芯片上的参考时钟之间的相位关系的时钟分配器电路
公开(公告)号：WO2004015743A3
公开(公告)日：2004-06-17
申请号：PCT/US0324315
申请日：2003-08-05
申请人： TIMELAB CORP
发明人： CARLEY ADAM L
IPC分类号： G06F1/10 , H03K5/13 , H03K5/15 , G06F17/50
CPC分类号： G06F1/10
摘要： A clock signal distributor circuit (12) for maintaining a phase relationship between one or more remote operating nodes (15, 17) and a reference clock on a chip, wherein there is a clock signal drive path and a clock signal sense path in a distribution limb (14, 16) for each remote node (15, 17). The clock signal distributor circuit (12) comprises a variable signal delay circuit in the clock signal drive path, a variable signal delay circuit in the clock signal sense path, and a feedback circuit that causes at least one variable signal delay circuit to change its signal delay based on phase of signal on the clock signal sense path.
摘要翻译：一种用于维持一个或多个远程操作节点（15,17）和芯片上的参考时钟之间的相位关系的时钟信号分配器电路（12），其中在分配中存在时钟信号驱动路径和时钟信号检测路径肢体（14,16），用于每个远程节点（15,17）。时钟信号分配器电路（12）包括时钟信号驱动路径中的可变信号延迟电路，时钟信号检测路径中的可变信号延迟电路和使至少一个可变信号延迟电路改变其信号的反馈电路基于时钟信号感测路径上的信号相位延迟。

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