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    • 3. 发明申请
    • DATA TRANSMISSION SYSTEMS WITH DC BALANCED CODE
    • 具有直流平衡码的数据传输系统
    • WO2005107199A3
    • 2006-03-02
    • PCT/IB2005001156
    • 2005-04-29
    • MELEXIS NVWOLLESWINKEL RICK
    • WOLLESWINKEL RICK
    • H03M5/08H04L25/49
    • H03M5/08
    • In a data transmission system, binary data is transmitted by transmitting alternate high and low pulses of defined durations wherein: a first binary data bit is encoded by a high or low pulse having a first defined duration; and wherein a second binary data bit is encoded by a high or low pulse having either a second defined duration or a third defined duration wherein the selection of the duration of pulse encoding a particular second data bit is determined as is necessary to maintain a substantially constant mean signal level in a transmitted data stream. In an alternative implementation, transmitted data is encoded as bit pairs, each bit pair comprises a sequence of high and low pulses, each pulse in each bit pair having a defined duration wherein each bit pair has an equal mean signal level. The data transmission method may be applied to low cost, low data rate systems such as building control systems, security access systems and stock control systems.
    • 在数据传输系统中,通过传送定义的持续时间的备选高和低脉冲来发送二进制数据,其中:第一二进制数据位由具有第一限定持续时间的高或低脉冲编码; 并且其中第二二进制数据位由具有第二定义持续时间或第三定义持续时间的高或低脉冲编码,其中确定对特定第二数据位的脉冲编码的持续时间的选择,以维持基本上恒定 传输数据流中的平均信号电平。 在替代实现中,发送的数据被编码为比特对,每个比特对包括高和低脉冲序列,每个比特对中的每个脉冲具有确定的持续时间,其中每个比特对具有相等的平均信号电平。 数据传输方法可以应用于低成本,低数据速率系统,例如建筑物控制系统,安全接入系统和库存控制系统。
    • 5. 发明申请
    • DIGITAL PULSE WIDTH CONTROLLED OSCILLATION MODULATOR
    • 数字脉冲宽度控制振荡调制器
    • WO2004086629A1
    • 2004-10-07
    • PCT/IB2004/000852
    • 2004-03-23
    • BANG & OLUFSEN ICEPOWER A/SNIELSEN, OLe, Nies
    • NIELSEN, OLe, Nies
    • H03M5/08
    • H03M5/08H03M3/506H03M7/3004H03M7/3028H03M7/304
    • A pulse width modulator (10) for converting a digital signal into a PWM signal, comprising a plurality of integrators (11) with integrator gains (12) arranged in series, a comparator (17) for comparing the output of the last integrator (11') with a reference, and thereby creating the PWM signal. The modulator further has means (13) for realizing self-oscillation at a desired switching frequency, and a feedback path (14) connected to a point down stream said comparator and leading to a plurality of summing points, each preceding one of said integrators, wherein the PWM signal is quantized in time by the clock frequency of the modulator, and wherein the integrator gains (12) are adapted to reduce any quantization noise.
    • 一种用于将数字信号转换为PWM信号的脉冲宽度调制器(10),包括具有串联布置的积分器增益(12)的多个积分器(11),比较器(17),用于比较最后一个积分器 '),从而产生PWM信号。 调制器还具有用于以期望的开关频率实现自振荡的装置(13)和连接到下游流的所述比较器并且导致多个求和点的反馈路径(14),每个求和点各自在所述积分器之一之前, 其中所述PWM信号在调制器的时钟频率上被量化,并且其中所述积分器增益(12)适于减少任何量化噪声。
    • 9. 发明申请
    • DUAL PHASE PULSE MODULATION SYSTEM
    • 双相脉冲调制系统
    • WO2005036805A3
    • 2005-07-21
    • PCT/US2004033342
    • 2004-10-08
    • ATMEL CORP
    • COHEN DANIEL SFAGAN JOHN L
    • H03M5/08H04B14/04
    • H04L25/4902H03M5/08H04L25/4904H04N1/00127H04N2201/0015H04N2201/0065
    • A system configured to transmit and receive data signals over a data link in serial fashion using dual phase pulse modulation (DPPM) is described. The data link may be, for example, a one or two wire unshielded twisted pair (UTP) cable. An exemplary system includes a configurable interface (301) able to accept parallel data from an external source, such as a microprocessor or an imaging device. The interface (301) is externally programmable for a particular data format. An encoder is coupled to the configurable interface (301) and converts parallel data into serial output data, the serial output data having high and low data pulses with each of the high and low data pulses encoded to have one of 2 distinct data pulse widths. The system further includes a decoder (303) coupled to the configurable interface (301), which is able to convert the serial input data into parallel data.
    • 描述了被配置为通过数据链路以串行方式使用双相位脉冲调制(DPPM)来发送和接收数据信号的系统。 数据链路可以是例如一根或两根非屏蔽双绞线(UTP)电缆。 示例性系统包括能够接收来自诸如微处理器或成像设备的外部源的并行数据的可配置接口(301)。 接口(301)可以在外部对特定数据格式进行编程。 编码器耦合到可配置接口(301)并且将并行数据转换为串行输出数据,串行输出数据具有高和低数据脉冲,其中每个高和低数据脉冲被编码为具有2个不同数据之一 脉冲宽度 该系统还包括耦合到可配置接口(301)的解码器(303),其能够将串行输入数据转换为并行数据。