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    • 1. 发明申请
      WO2006083555A2 DIGITALLY PROGRAMMABLE DELAY CIRCUIT WITH PROCESS POINT TRACKING 审中-公开
    • DIGITALLY PROGRAMMABLE DELAY CIRCUIT WITH PROCESS POINT TRACKING
    • 具有过程点跟踪的数字可编程延迟电路
    • WO2006083555A2
    • 2006-08-10
    • PCT/US2006/001727
    • 2006-01-19
    • TIMELAB CORPORATION , CARLEY, Adam, L. , ALLEN, Daniel, J. , MANDRY, James, E.
    • CARLEY, Adam, L. , ALLEN, Daniel, J. , MANDRY, James, E.
    • H03K17/296
    • H03K5/133 , H03K2005/00065 , H03K2005/00221
    • A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay amount to the edge, wherein the delay control signal is based on a desired delay amount and a measure of instantaneous process, voltage and temperature conditions of an integrated circuit in which the plurality of transistors are implemented. A selector circuit is responsive to the delay control signal and converts the delay control signal into one or more transistor selection signals to activate one or more of the plurality of transistors. The plurality of transistors may comprise a first sub-circuit having a plurality of transistors of a first type (e.g., P- type) connected in parallel with each other in a ladder configuration, and a second sub-circuit comprising a plurality of transistors of a second type (e.g., N-type) connected in parallel with each other and in a ladder configuration. The overall delay imposed on the edge after it has passed through both sub-circuits has delay contributions from both types of transistors. The delay circuit may have enhanced performance because of finer delay control granularity by providing a first circuit stage that comprises a plurality of transistors for relatively fine delay adjustment to the edge and a second circuit stage that comprises a plurality of transistors for relatively coarse delay adjustment to the edge. A combination of one or more of the transistors in the first and second circuit stages may be selected to produce numerous steps or increments of delay adjustability.
    • 一种数字可编程延迟电路，包括彼此并联连接的多个晶体管以及承载具有待延迟边缘的信号的线。 通过延迟控制信号选择一个或多个晶体管，以对边缘施加延迟量，其中延迟控制信号基于期望的延迟量和集成电路的瞬时过程，电压和温度条件的测量 多个晶体管被实现。 选择器电路响应延迟控制信号并将延迟控制信号转换成一个或多个晶体管选择信号以激活多个晶体管中的一个或多个。 多个晶体管可以包括具有第一类型（例如，P型）的多个晶体管的第一子电路，其以梯形配置彼此并联连接，第二子电路包括多个晶体管， 第二类型（例如，N型），彼此并联并且以梯形结构连接。 在通过两个子电路之后施加在边缘上的总体延迟具有来自两种类型的晶体管的延迟贡献。 延迟电路可以通过提供包括多个用于对边缘进行相对精细的延迟调整的多个晶体管的第一电路级，由于更精细的延迟控制粒度而具有增强的性能，第二电路级包括用于相对粗略延迟调整的多个晶体管 边缘。 可以选择第一和第二电路级中的一个或多个晶体管的组合以产生许多延迟可调性的步骤或增量。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明申请
      WO2003084051A2 AN ARBITRARY WAVEFORM SYNTHESIZER USING A FREE-RUNNING RING OSCILLATOR 审中-公开
    • AN ARBITRARY WAVEFORM SYNTHESIZER USING A FREE-RUNNING RING OSCILLATOR
    • 使用自由运行振荡器的仲裁波形合成器
    • WO2003084051A2
    • 2003-10-09
    • PCT/US2002/009155
    • 2002-03-25
    • TIMELAB CORPORATION , CARLEY, Adam, L.
    • CARLEY, Adam, L.
    • H03B
    • G06F1/022 , G06F1/025 , H03K5/133 , H03K5/159 , H03L7/0814 , H03L7/16
    • The waveform generator inlcudes a free-running ring oscillator, an algebra module, a switching module and an output module. The free-running ring oscillator includes a plurality of delay elements connected in a loop and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module generates an output signal indicating a first rising edge of the arbitrary waveform in response to an input signal. The switching module includes a switch input port in electrical communication with the algebra data output port, a lurality of switch tap input ports in electrical communication with the free-running ring oscillator taps and switch output port. At the switch output port, the switch module provides a first transition signal selected from one of the plurality of free running ring oscillator taps in response to the signal indicative of a first rising edge received at the switch input port. The output module has at ransision signal input port in electrical communication with the switch output port, a window input port in electrical communication with the algebra data output port and a waveform output port in electrical communication with the clock input port of the algebra module. The output module creates an arbitrary waveform at the waveform output port in response to the first transition signal received at the transmition signal input port of the output module and the signal of a first rising edge received at the window input port.
    • 波形发生器包括一个自由运行的环形振荡器，一个代数模块，一个开关模块和一个输出模块。 自由运行的环形振荡器包括以循环连接的多个延迟元件和设置在延迟元件之间的多个抽头，每个抽头提供唯一的阶段的振荡转换信号。 代数模块响应于输入信号产生指示任意波形的第一上升沿的输出信号。 开关模块包括与代数数据输出端口电连通的开关输入端口，与自由运行的环形振荡器抽头和开关输出端口电连通的开关抽头输入端口。 在开关输出端口处，响应于指示在开关输入端口处接收到的第一上升沿的信号，开关模块提供从多个自由运行环形振荡器抽头之一中选择的第一转换信号。 输出模块具有与开关输出端口电连接的转换信号输入端口，与代数数据输出端口电气通信的窗口输入端口和与代数模块的时钟输入端口电气通信的波形输出端口。 输出模块响应于在输出模块的发射信号输入端口处接收到的第一转换信号和在窗口输入端口接收的第一上升沿的信号，在波形输出端口处产生任意波形。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明申请
      WO2006044586A2 SPREAD SPECTRUM CLOCK SIGNAL GENERATION SYSTEM AND METHOD 审中-公开
    • SPREAD SPECTRUM CLOCK SIGNAL GENERATION SYSTEM AND METHOD
    • 传播频谱信号发生系统和方法
    • WO2006044586A2
    • 2006-04-27
    • PCT/US2005/036918
    • 2005-10-12
    • TIMELAB CORPORATION , CARLEY, Adam, L. , ALLEN, Daniel, J.
    • CARLEY, Adam, L. , ALLEN, Daniel, J.
    • H04B1/69
    • G06F1/08
    • A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal. The programmable modulator is coupled to an arbitrary waveform synthesizer that generates timing for edges of the clock signal based on the edge position values. A variety of modulations can be imposed on the clock signal using these techniques, including triangle wave modulation, near-triangle modulation, random and pseudo-random modulation.
    • 一种用于产生具有扩频调制的时钟信号的系统和方法。 该方法涉及通过从针对每个边缘的定时的数字表示产生时钟信号的边缘的边缘位置来产生时钟信号，以将扩频调制传递给时钟信号。 提供了一种可编程调制器，其基于时变周期值和时变占空比值中的至少一个，生成表示时钟信号的边沿的边缘位置的数字值。 可编程调制器可以包括产生时变数字周期值的称为周期调制电路的第一电路和产生时变数字占空比值的称为占空比调制电路的第二电路。 处理时变周期值和时变占空比值以产生指定时钟信号的边沿位置的数字边沿位置值。 可编程调制器耦合到任意波形合成器，其基于边缘位置值产生时钟信号的边沿的定时。 使用这些技术可以对时钟信号施加各种调制，包括三角波调制，近三角调制，随机和伪随机调制。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明申请
      WO2005077034A2 HIGH SPEED SERIALIZER-DESERIALIZER 审中-公开
    • HIGH SPEED SERIALIZER-DESERIALIZER
    • 高速串联器 - DESERIALIZER
    • WO2005077034A2
    • 2005-08-25
    • PCT/US2005003992
    • 2005-02-09
    • TIMELAB CORP , CARLEY ADAM L
    • CARLEY ADAM L
    • H03M5/08 , H03M7/00
    • H03M5/08
    • A high speed serializer-deserializer (SerDes) that passes significantly more data through a channel for a given analog bandwidth and signal-to-noise ratio. This SerDes technique involves converting a plurality of bits to be transferred to positions of edges of a waveform that is transmitted over at least one transmission wire from a source to a destination. The plurality of bits are converted to edges in order to position edges such that more than k inter-edge spacings are possible over a range of spacings between T and kT, where k is a real number greater than 1 and T is the minimum spacing between consecutive edges. An edge position translation scheme that maps patterns in a stream of input bits to a corresponding spacing between a rising edge and a falling edge of the waveform, or between a falling edge and a rising edge of the waveform. The bits are recovered at the destination by detecting the edges in the received waveform at the destination and driving a stream of binary numbers representing time intervals between detected consecutive edges (inter-edge spacings). The stream of binary numbers is decoded according to the edge position translation scheme to recover corresponding bits.
    • 一种高速串行器 - 解串器（SerDes），通过通道显示更多的数据，以获得给定的模拟带宽和信噪比。 该SerDes技术涉及将要传送的多个比特转换到通过至少一根传输线从源传输到目的地的波形边缘的位置。 将多个位转换为边缘以便定位边缘，使得在T和kT之间的间隔范围内多于k个边缘间隔是可能的，其中k是大于1的实数，T是大于1的实数，并且T是 连续边缘 边缘位置转换方案，将输入比特流中的图形映射到波形的上升沿和下降沿之间的相应间隔，或波形的下降沿和上升沿之间。 通过检测目的地的接收波形中的边缘，并且驱动表示检测到的连续边缘之间的时间间隔（边缘间隔）的二进制数据流，在目的地恢复比特。 根据边缘位置转换方案对二进制数字流进行解码，以恢复相应的位。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明申请
      WO2006083556A3 DELAY CIRCUIT FOR SYNCHRONIZING ARRIVAL OF A CLOCK SIGNAL AT DIFFERENT CIRCUIT BOARD POINTS 审中-公开
    • DELAY CIRCUIT FOR SYNCHRONIZING ARRIVAL OF A CLOCK SIGNAL AT DIFFERENT CIRCUIT BOARD POINTS
    • 用于同步不同电路板时钟信号的延迟电路
    • WO2006083556A3
    • 2007-01-04
    • PCT/US2006001728
    • 2006-01-19
    • TIMELAB CORP , CARLEY ADAM L , ALLEN DANIEL J , MANDRY JAMES E
    • CARLEY ADAM L , ALLEN DANIEL J , MANDRY JAMES E
    • G06F1/04
    • H03H11/265
    • A clock signal generation system and method to distribute at least one clock signal to a plurality of points on a circuit board using a plurality of digitally programmable delay circuits (10) each of which delays the clock signal (Clockln) by a desired amount so as to synchronize arrival of the clock signal when distributed to each of the plurality of points on the circuit. Each digitally programmable delay circuits (10) comprises a plurality of circuit stages (100(l)-100(N)) connected in series with each other. Each circuit stage comprises a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other, and a plurality of transistors of a second type (c.g., N-type) connected in parallel with each other in each circuit stage, one or more of the plurality of transistors of the first type are selected to delay a rising edge, and one or more of the plurality of transistors of a second type are selected to delay a falling edge.
    • 一种时钟信号产生系统和方法，用于使用多个数字可编程延迟电路（10）将至少一个时钟信号分配到电路板上的多个点，每个延迟电路将时钟信号（Clock1n）延迟期望的量，以便 当分配给电路上的多个点中的每个点时，同步时钟信号的到达。 每个数字可编程延迟电路（10）包括彼此串联连接的多个电路级（100（1）-100（N））。 每个电路级包括彼此并联连接的多个第一类型的晶体管（例如，P型），以及在每个电路平台中彼此并联连接的第二类型（cg，N型）的多个晶体管 选择第一类型的多个晶体管中的一个或多个以延迟上升沿，并且选择第二类型的多个晶体管中的一个或多个延迟下降沿。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明申请
      WO2006083556A2 DELAY CIRCUIT FOR SYNCHRONIZING ARRIVAL OF A CLOCK SIGNAL AT DIFFERENT CIRCUIT BOARD POINTS 审中-公开
    • DELAY CIRCUIT FOR SYNCHRONIZING ARRIVAL OF A CLOCK SIGNAL AT DIFFERENT CIRCUIT BOARD POINTS
    • 用于同步不同电路板时钟信号的延迟电路
    • WO2006083556A2
    • 2006-08-10
    • PCT/US2006/001728
    • 2006-01-19
    • TIMELAB CORPORATION , CARLEY, Adam, L. , ALLEN, Daniel, J. , MANDRY, James, E.
    • CARLEY, Adam, L. , ALLEN, Daniel, J. , MANDRY, James, E.
    • H03H11/26
    • H03H11/265
    • A clock signal generation system and method to distribute at least one clock signal to a plurality of points on a circuit board using a plurality of digitally programmable delay circuits each of which delays the clock signal by a desired amount so as to synchronize arrival of the clock signal when distributed to each of the plurality of points on the circuit. Each digitally programmable delay circuit comprises a plurality of circuit stages connected in series with each other. Each circuit stage comprises a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other, and a plurality of transistors of a second type (e.g., N-type) connected in parallel with each other. In each circuit stage, one or more of the plurality of transistors of the first type are selected to delay a rising edge, and one or more of the plurality of transistors of a second type are selected to delay a falling edge.
    • 一种时钟信号产生系统和方法，用于使用多个数字可编程延迟电路将至少一个时钟信号分配到电路板上的多个点，每个延迟电路将时钟信号延迟期望量，以便同步时钟的到达 当分配给电路上的多个点中的每一个时，信号。 每个数字可编程延迟电路包括彼此串联连接的多个电路级。 每个电路级包括彼此并联连接的第一类型（例如P型）的多个晶体管，以及彼此并联连接的多个第二类型晶体管（例如N型）。 在每个电路级中，选择第一类型的多个晶体管中的一个或多个以延迟上升沿，并且选择第二类型的多个晶体管中的一个或多个以延迟下降沿。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明申请
      WO2006044586A3 SPREAD SPECTRUM CLOCK SIGNAL GENERATION SYSTEM AND METHOD 审中-公开
    • SPREAD SPECTRUM CLOCK SIGNAL GENERATION SYSTEM AND METHOD
    • 传播频谱信号发生系统和方法
    • WO2006044586A3
    • 2007-02-01
    • PCT/US2005036918
    • 2005-10-12
    • TIMELAB CORP , CARLEY ADAM L , ALLEN DANIEL J
    • CARLEY ADAM L , ALLEN DANIEL J
    • H04B1/69
    • G06F1/08
    • A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal. The programmable modulator is coupled to an arbitrary waveform synthesizer that generates timing for edges of the clock signal based on the edge position values. A variety of modulations can be imposed on the clock signal using these techniques, including triangle wave modulation, near-triangle modulation, random and pseudo-random modulation.
    • 一种用于产生具有扩频调制的时钟信号的系统和方法。 该方法涉及通过从针对每个边缘的定时的数字表示产生时钟信号的边缘的边缘位置来产生时钟信号，以将扩频调制传递给时钟信号。 提供了一种可编程调制器，其基于时变周期值和时变占空比值中的至少一个，生成表示时钟信号的边沿的边缘位置的数字值。 可编程调制器可以包括产生时变数字周期值的称为周期调制电路的第一电路和产生时变数字占空比值的称为占空比调制电路的第二电路。 处理时变周期值和时变占空比值以产生指定时钟信号的边沿位置的数字边沿位置值。 可编程调制器耦合到任意波形合成器，其基于边缘位置值产生时钟信号的边沿的定时。 使用这些技术可以对时钟信号施加各种调制，包括三角波调制，近三角调制，随机和伪随机调制。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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