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1. 发明申请

WO1992022926A1 A MONOLITHIC SEMICONDUCTOR COMPONENT FOR TRANSIENT VOLTAGE SUPPRESSION 审中-公开
标题翻译：用于瞬态电压抑制的单片半导体元件
公开(公告)号：WO1992022926A1
公开(公告)日：1992-12-23
申请号：PCT/GB1992001055
申请日：1992-06-11
申请人： TEXAS INSTRUMENTS LIMITED
发明人： TEXAS INSTRUMENTS LIMITED , BYATT, Stephen, Wilton
IPC分类号： H01L29/74
CPC分类号： H01L29/87 , H01L29/7416
摘要： A monolithic semiconductor component including a P-type body and an N-type body having an interface with each other, in which a part of the P-type body and a part of the N-type body are the inner P and N regions of a PNPN device, another part of the P-type body and another part of the N-type body are the P and N regions of a PN diode, and the part of the N-type body in the PNPN device is thicker than the part of that body in the PN diode, where thickness is measured in the direction of current flow through the N-type body.

2. 发明申请

WO1996004685A1 A POWER SEMICONDUCTOR DEVICE 审中-公开
标题翻译：功率半导体器件
公开(公告)号：WO1996004685A1
公开(公告)日：1996-02-15
申请号：PCT/GB1995001857
申请日：1995-08-04
申请人： TEXAS INSTRUMENTS LIMITED , TEXAS INSTRUMENTS INCORPORATED , GARNHAM, David, Arthur , RUTGERS, Koenraad, Teunis, Francis
发明人： TEXAS INSTRUMENTS LIMITED , TEXAS INSTRUMENTS INCORPORATED
IPC分类号： H01L29/32
CPC分类号： H01L29/66295 , H01L21/221 , H01L29/1004 , H01L29/102 , H01L29/32
摘要： A semiconductor device having two or more p-n junctions, being in particular a bipolar transistor or a thyristor. The device has a gold ion implant (14) in a region of the device between two of or the two p-n junctions, which region is the base (2) in the case of a bipolar transistor, located away from the current carrying active region of the device. The device has a low resistance and may be turned off rapidly because the implanted gold provides recombination centres which act as a sink for carriers drawing them from the active region.
摘要翻译：具有两个或更多个p-n结的半导体器件，特别是双极晶体管或晶闸管。器件在两个或两个pn结之间的器件的区域中具有金离子注入（14），在双极晶体管的情况下，该区域是基极（2），位于远离载流有源区装置。该器件具有低电阻并且可能被快速关闭，因为注入的金提供复合中心，其用作用于从活性区域吸取它们的载体的汇点。

3. 发明申请

WO1992022927A2 A SEMICONDUCTOR COMPONENT FOR TRANSIENT VOLTAGE LIMITING 审中-公开
标题翻译：瞬态电压限制的半导体元件
公开(公告)号：WO1992022927A2
公开(公告)日：1992-12-23
申请号：PCT/GB1992001056
申请日：1992-06-11
申请人： TEXAS INSTRUMENTS LIMITED , BYATT, Stephen, Wilton , MAYTUM, Michael, John
发明人： TEXAS INSTRUMENTS LIMITED
IPC分类号： H01L29/74
CPC分类号： H01L29/747 , H01L27/0814 , H01L27/0817 , H01L29/7416 , H01L29/87
摘要： A semiconductor component for limiting transient voltages on the signal or other supply lines of a system, includes, in a common semiconductor body, a plurality of multi-junction diodes connected in the same sense between a common terminal and respective input means which are for connection to the respective supply lines of the system, and a respective further diode connected in shunt with each multi-junction diode with the opposite sense to the multi-junction diode.

4. 发明申请

WO1992022171A1 METHOD AND APPARATUS FOR DETECTING A SEQUENCE OF CLOCK REFERENCE PULSES 审中-公开
标题翻译：用于检测时钟参考脉冲序列的方法和装置
公开(公告)号：WO1992022171A1
公开(公告)日：1992-12-10
申请号：PCT/GB1992001018
申请日：1992-06-05
申请人： TEXAS INSTRUMENTS LIMITED
发明人： TEXAS INSTRUMENTS LIMITED , KORATZINOS, Vassilis
IPC分类号： H04N07/087
CPC分类号： H04L7/0331 , H03L7/0992 , H04L7/044 , H04L7/046 , H04N7/0352
摘要： A clock run-in sequence of equally spaced similar input pulses is sampled at a much higher frequency and the samples converted to single bits. The resulting sequence of bits is fed into a shift register (7) the stages of which are connected to logic means (8) which produces indications when the bits stored in the register represent a centrally located input pulse or space between input pulses. The clock pulses driving the sampler are fed to frequency divider (18) which produces the local clock signal. The local clock signal is synchronised with the clock run-in sequence by deriving the average phase of the frequency divider at a number of indications and adjusting the phase of the divider accordingly.
摘要翻译：等间隔相似的输入脉冲的时钟延迟序列以更高的频率被采样，并且采样转换为单个位。所得到的比特序列被馈送到移位寄存器（7），其移位寄存器（7）连接到逻辑装置（8），当存储在寄存器中的位表示输入脉冲之间的中心位置的输入脉冲或空间时，该逻辑装置产生指示。驱动采样器的时钟脉冲被馈送到产生本地时钟信号的分频器（18）。本地时钟信号与时钟输入顺序同步，通过在多个指示上导出分频器的平均相位并相应地调整分频器的相位。

5. 发明申请

WO1997024764A1 INTEGRATED SYSTEM PACKAGE 审中-公开
标题翻译：集成系统包
公开(公告)号：WO1997024764A1
公开(公告)日：1997-07-10
申请号：PCT/GB1997000008
申请日：1997-01-02
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS LIMITED
发明人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS LIMITED , ORTHMANN, Kurt , MITTERTRAINER, Peter , HOFFMANN, Johann
IPC分类号： H01L25/16
CPC分类号： H01L25/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2924/01322 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： A standard package is provided in which circuit components (10) and non-integrated circuit components (20, 30, 40) are electrically connected together and then overmoulded (70). The components may be coupled together on a lead frame (60). The standard package may provide a desired electrical function by itself or it may be coupled together with other overmoulded packages or additional non-overmoulded electronic components.
摘要翻译：提供了一种标准封装，其中电路部件（10）和非集成电路部件（20,30,40）电连接在一起，然后被包覆成型（70）。组件可以在引线框架（60）上耦合在一起。标准包装可以自己提供期望的电功能，或者可以与其它包覆成型的包装或附加的非包覆成型的电子部件耦合在一起。

6. 发明申请

WO1992022959A1 A VOLTAGE COMPARATOR 审中-公开
标题翻译：电压比较器
公开(公告)号：WO1992022959A1
公开(公告)日：1992-12-23
申请号：PCT/GB1992001084
申请日：1992-06-17
申请人： TEXAS INSTRUMENTS LIMITED
发明人： TEXAS INSTRUMENTS LIMITED , HALL, Andrew, Medlicott
IPC分类号： H03K03/356
CPC分类号： H03K3/356139 , H03K3/356043
摘要： A voltage comparator, consisting of a network of voltage-to-current converters connected together by means of switches, operable to provide an output signal indicating the relative magnitudes of two input voltages.

7. 发明申请

WO1996003775A1 METHOD AND APPARATUS FOR AFFIXING SPHERES TO A FOIL MATRIX 审中-公开
标题翻译：用于将球体固定到一个基础矩阵的方法和装置
公开(公告)号：WO1996003775A1
公开(公告)日：1996-02-08
申请号：PCT/GB1995001710
申请日：1995-07-20
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS LIMITED
发明人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS LIMITED , HOTCHKISS, Gregory , LEVINE, Jules, David , SHARROCK, Paul, Ray
IPC分类号： H01L31/18
CPC分类号： H01L31/03529 , H01L31/042 , H01L31/1804 , H01L31/1876 , H01L2924/0002 , Y02E10/547 , Y02P70/521 , H01L2924/00
摘要： An improved method of affixing spheres (4) to a foil matrix (2) is described herein. First, a cell sandwich (32) is prepared. This cell sandwich (32) includes spheres (4) mounted on a foil matrix (2) which are disposed between upper and lower pressure pads (34 and 36). The cell sandwich (32) is then heated (e.g., to about 530 DEG C). The spheres (4) are then affixed to the foil matrix (2) by directing the cell sandwich (32) through a roll press (48) which compresses the heated cell sandwich (32).
摘要翻译：本文描述了将球体（4）固定到箔基质（2）的改进方法。首先，准备细胞夹心（32）。该电池夹层（32）包括安装在箔基体（2）上的球体（4），它们设置在上压力垫和下压力垫（34和36）之间。然后将电池夹层（32）加热（例如至约530℃）。然后通过将细胞夹层（32）引导通过压制加热的细胞夹心（32）的辊压机（48）将球体（4）固定到箔基质（2）上。

8. 发明申请

WO1995030227A1 A METHOD AND APPARATUS FOR TESTING A MEMORY CIRCUIT WITH PARALLEL BLOCK WRITE OPERATION 审中-公开
标题翻译：用于测试具有并行块写操作的存储器电路的方法和装置
公开(公告)号：WO1995030227A1
公开(公告)日：1995-11-09
申请号：PCT/GB1995000978
申请日：1995-04-28
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS LIMITED
发明人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS LIMITED , DORNEY, Timothy, Dominic , BALISTRERI, Anthony, Michael
IPC分类号： G11C29/00
CPC分类号： G11C29/28
摘要： An integrated circuit memory device (21) includes plural input/output pins (30, 127 and others) and plural arrays of addressable storage cells (31-46). A set of circuits (51, 68, 70, 71-86, 90) provides access to a unique storage location in each array (31-46) through a given row and column address. A writing circuit (47, 68, 70, 71-86, 91-106, 131-146), designed for test, provides in parallel plural copies of a test data bit. The test data bit is applied through a single pin (30) and a common data-in lead (68), for storage in an addressed storage cell in each of the arrays. A readout circuit (110, 111, 112, 171, 127, 201-216, 131-146) is arranged for reading out the stored test data bit from the addressed storage cell in each of the arrays (31-46). The writing circuit, while in a block write test mode, stores the test data bit on the common data-in lead (68) in a block of address locations in each array (31-46).
摘要翻译：集成电路存储器件（21）包括多个输入/输出引脚（30,127等）和多个可寻址存储单元阵列（31-46）。一组电路（51,68,70,71-86,90）通过给定的行和列地址提供对每个阵列（31-46）中唯一存储位置的访问。设计用于测试的写入电路（47,68,70,71-86,91-106,131-146）并行提供测试数据位的多个副本。测试数据位通过单个引脚（30）和公共数据输入引线（68）施加，用于存储在每个阵列中的寻址存储单元中。读出电路（110,111,112,171,127,201-216,131-146）用于从每个阵列（31-46）中的所寻址的存储单元读出存储的测试数据位。写入电路在块写入测试模式下，将测试数据位存储在每个阵列（31-46）中的地址位置块中的公共数据引入线（68）中。

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