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1. 发明申请

WO2008151164A1 N-CANDIDATE DEPTH-FIRST DECODING 审中-公开
标题翻译： N-CANDIDATE深度解码
公开(公告)号：WO2008151164A1
公开(公告)日：2008-12-11
申请号：PCT/US2008/065584
申请日：2008-06-02
申请人： TEXAS INSTRUMENTS INCORPORATED , KIM, Hun-seok , LEE, Seok-jun , GOEL, Manish
发明人： KIM, Hun-seok , LEE, Seok-jun , GOEL, Manish
IPC分类号： H04J15/00 , H04B7/04
CPC分类号： H04L25/03203 , H04L25/03318 , H04L2025/03414 , H04L2025/03426
摘要： The problem outlined above may at least in part be addressed by N-Candidate Depth- First Decoding methods and systems that employ such methods. In some embodiments, the method includes receiving data (1204) representing a vector of receive signals detected by multiple receive transceivers; performing an N-candidate, depth-first search on the data to obtain an estimated constellation point (1206); and providing a user data stream based at least in part on the estimated constellation point (1208). In some embodiments the system includes a multiple-input multiple-output decoder. The decoder is configured to perform an N- candidate, depth-first search as part of converting a receive signal into a data stream.
摘要翻译：上述问题可能至少部分地由采用这种方法的N-Candidate Depth-First Decoding方法和系统来解决。在一些实施例中，该方法包括接收表示由多个接收收发器检测到的接收信号的向量的数据（1204）对所述数据执行N候选深度优先搜索以获得估计的星座点（1206）; 以及至少部分地基于估计的星座点（1208）提供用户数据流。在一些实施例中，系统包括多输入多输出解码器。解码器被配置为执行N-候选，深度优先搜索，作为将接收信号转换为数据流的一部分。

2. 发明申请

WO2008151165A1 SCALABLE VLSI ARCHITECTURE FOR K-BEST BREADTH-FIRST DECODING 审中-公开
标题翻译：可扩展的VLSI架构，用于K-BEST BREADTH-FIRD解码
公开(公告)号：WO2008151165A1
公开(公告)日：2008-12-11
申请号：PCT/US2008/065585
申请日：2008-06-02
申请人： TEXAS INSTRUMENTS INCORPORATED , KIM, Hun-seok , LEE, Seok-jun , GOEL, Manish
发明人： KIM, Hun-seok , LEE, Seok-jun , GOEL, Manish
IPC分类号： H04J15/00 , H04B7/04
CPC分类号： G06F17/505 , H04L1/0045 , H04L25/03203 , H04L2025/03426
摘要： In some embodiments, a device includes a multiple-input multiple-output ("MIMO") decoder module coupled to a first log-likelihood-ratio ("LLR") computing unit. The decoder module includes at least one processing unit and at least one sorting unit. The decoder module preferably uses a K-best breadth-first search method to decode data from MIMO sources. In some embodiments, a method includes receiving data representing a vector of receive signal samples detected by multiple receive transceivers (1604). The method further includes performing a K-best breadth- first search on the data to obtain an estimated constellation point (1606). The method further includes providing a user data stream based at least in part on the estimated constellation point (1608).
摘要翻译：在一些实施例中，设备包括耦合到第一对数似然比（“LLR”）计算单元的多输入多输出（“MIMO”）解码器模块。解码器模块包括至少一个处理单元和至少一个分类单元。解码器模块优选地使用K最佳宽度优先搜索方法来解码来自MIMO源的数据。在一些实施例中，一种方法包括接收表示由多个接收收发器检测到的接收信号样本的向量的数据（1604）。该方法还包括对数据执行K最佳宽度优先搜索以获得估计的星座点（1606）。该方法还包括至少部分地基于估计的星座点（1608）提供用户数据流。

3. 发明申请

WO2007059489A3 CASCADED RADIX ARCHITECTURE FOR HIGH-SPEED VITERBI DECODER 审中-公开
公开(公告)号：WO2007059489A3
公开(公告)日：2007-05-24
申请号：PCT/US2006/060878
申请日：2006-11-14
申请人： TEXAS INSTRUMENTS INCORPORATED , LINGAM, Srinivas , LEE, Seok-jun , BATRA, Anuj , GOEL, Manish
发明人： LINGAM, Srinivas , LEE, Seok-jun , BATRA, Anuj , GOEL, Manish
IPC分类号： H03M13/03
摘要： A Viterbi decoder includes a branch metric unit (25) for generating branch metrics between two states at two different time periods, a traceback unit (27), a traceback memory (28) and an add-compare-select circuit unit (26). The add-compare-select circuit includes a plurality of cascaded add-compare-select sub-circuits, each add-compare-select sub-circuit calculating a path metric responsive to a plurality of branch metrics from the branch metric unit and a plurality of pre-calculated path metrics, where at least one of the add-compare-select sub-circuits receives a set of pre-calculated path metrics from another one of the add-compare-select sub-circuits.

4. 发明申请

WO2006025996A2 CONCATENATED CODING OF THE MULTI-BAND ORTHOGONAL FREQUENCY DIVISION MODULATION SYSTEM 审中-公开
标题翻译：多波段正交频分调制系统的定义编码
公开(公告)号：WO2006025996A2
公开(公告)日：2006-03-09
申请号：PCT/US2005/026876
申请日：2005-07-28
申请人： TEXAS INSTRUMENTS INCORPORATED , BALAKRISHNAN, Jaiganesh , LINGAM, Srinivas , GOEL, Manish , BATRA, Anuj
发明人： BALAKRISHNAN, Jaiganesh , LINGAM, Srinivas , GOEL, Manish , BATRA, Anuj
IPC分类号： H04L23/02 , H04K1/10 , H04L27/04
CPC分类号： H04K1/00 , H03M13/1102 , H03M13/15 , H03M13/23 , H03M13/2936 , H03M13/2957 , H03M13/618 , H04L1/0041 , H04L1/0057 , H04L1/0059 , H04L1/0065 , H04L1/0072 , H04L1/04 , H04L5/023 , H04L27/2602 , H04L27/2608 , H04L2001/0098
摘要： The present disclosure is directed to a transmitter that includes a first block encoder 450 operable to block encode at least a first portion of a multi-band orthogonal frequency division modulation signal. The first block encoder 450 also includes a convolution encoder 304 operable to convolution encode the output of the first block encoder 450. A method of communicating is also disclosed. The method comprises block encoding a first portion of a message to produce a first outer code word. The method includes convolution encoding the first outer code word to produce a first inner code word. The method also includes transmitting the first inner code word as part of a multiband orthogonal frequency division modulation signal.
摘要翻译：本公开涉及一种发射机，其包括第一块编码器450，第一块编码器450可操作用于块化至少编码多频带正交频分调制信号的第一部分。第一块编码器450还包括可用于对第一块编码器450的输出进行卷积编码的卷积编码器304.还公开了一种通信方法。该方法包括对消息的第一部分进行块编码以产生第一外码字。该方法包括对第一外码字进行卷积编码以产生第一内码字。该方法还包括作为多频带正交频分调制信号的一部分发送第一内码字。

5. 发明申请

WO2004077276A2 ARCHITECTURE AND METHOD FOR PERFORMING A FAST FOURIER TRANSFORM AND OFDM RECEIVER EMPLOYING THE SAME 审中-公开
标题翻译：执行快速傅里叶变换的方法和方法以及使用其的OFDM接收器
公开(公告)号：WO2004077276A2
公开(公告)日：2004-09-10
申请号：PCT/US2004/006025
申请日：2004-02-27
申请人： TEXAS INSTRUMENTS INCORPORATED , GOEL, Manish
发明人： GOEL, Manish
IPC分类号： G06F
CPC分类号： H04L27/265 , G06F17/142
摘要： The present invention is directed to a fast Fourier transform (FFT) architecture. In one embodiment, the FFT architecture includes a pipeline segment having a plurality of data-independent pipelines that receive different time-domain data samples and generate therefrom corresponding intermediate results. Additionally, the FFT architecture also includes a parallel segment, coupled to all of the pipelines, that receives the corresponding intermediate results and generates therefrom corresponding frequency-domain results.
摘要翻译：本发明涉及快速傅里叶变换（FFT）架构。在一个实施例中，FFT架构包括具有多个独立于数据的管线的流水线段，其接收不同的时域数据采样并从中产生相应的中间结果。此外，FFT架构还包括耦合到所有管线的并行段，其接收对应的中间结果并从其产生相应的频域结果。

6. 发明申请

WO2005081416A1 SCALABLE, COOPERATIVE, WIRELESS NETWORKING FOR MOBILE CONNECTIVITY 审中-公开
标题翻译：可扩展的，合作的，无线网络的移动连接
公开(公告)号：WO2005081416A1
公开(公告)日：2005-09-01
申请号：PCT/US2005/005515
申请日：2005-02-22
申请人： TEXAS INSTRUMENTS INCORPORATED , BATRA, Anuj , BELK, Nathan, R. , DABAK, Anand, G. , DIRENZO, Micahel, T. , GOEL, Manish , HO, Jin, Meng , HOSUR, Srinath , LU, Xiaolin , MAGEE, David, P. , SHAVER, Donald, P. , YAMAGUCHI, Hirohisa
发明人： BATRA, Anuj , BELK, Nathan, R. , DABAK, Anand, G. , DIRENZO, Micahel, T. , GOEL, Manish , HO, Jin, Meng , HOSUR, Srinath , LU, Xiaolin , MAGEE, David, P. , SHAVER, Donald, P. , YAMAGUCHI, Hirohisa
IPC分类号： H04B1/38
CPC分类号： H04B1/0003 , H04B1/40 , H04B1/406
摘要： A wireless transceiver (10) is provided that includes a configurable analog component (14) and a controller portion (18). The configurable analog component (14) is operable to receive an input radio frequency signal and to transmit the output radio frequency signal. The controller portion (18) is operable to promote adjustment of a bandwidth of the configurable analog component (14) from at least a first bandwidth to a second bandwidth.
摘要翻译：提供了一种无线收发器（10），其包括可配置模拟组件（14）和控制器部分（18）。可配置模拟组件（14）可操作以接收输入射频信号并发射输出射频信号。控制器部分（18）可操作以促进将可配置模拟组件（14）的带宽从至少第一带宽调整到第二带宽。

7. 发明申请

WO2009005897A1 MEMBRANE-BASED HYBRID PROCESS FOR SEPARATION OF MIXTURES OF ORGANICS, SOLIDS, AND WATER 审中-公开
标题翻译：用于分离有机物，固体和水混合物的基于膜的混合工艺
公开(公告)号：WO2009005897A1
公开(公告)日：2009-01-08
申请号：PCT/US2008/063162
申请日：2008-05-09
申请人： I3 NANOTEC LLC , GOEL, Manish , MITTAL, Chetan, P.
发明人： GOEL, Manish , MITTAL, Chetan, P.
IPC分类号： B01D3/02
CPC分类号： B01D3/145 , B01D3/002 , B01D3/14 , B01D61/025 , B01D61/027 , B01D61/145 , B01D61/147 , B01D61/362 , B01D61/58
摘要： A system and process that are a hybrid of distillation and membrane separations offers a highly efficient means of separating a fluid feed mixture into organic, solid, and aqueous components. The distillation section is followed by two membrane separation sections operated in parallel, with the distillation section separating the feed mixture into an organics-rich fraction and an organics-depleted and solids-rich fraction. One membrane section operates on the organics-rich fraction and separates it into a more organics-rich sub-fraction and a water-rich, organics-depleted sub-fraction, while the other membrane section operates on the organics-depleted, solids-rich fraction from the distillation section and separates it into a solids-rich sub-fraction and a solids-depleted, water-rich sub-fraction.
摘要翻译：作为蒸馏和膜分离的混合物的系统和方法提供了将流体进料混合物分离成有机，固体和水性组分的高效手段。蒸馏段之后是两个平行操作的膜分离段，蒸馏段将进料混合物分离成富有机物部分和富有机物的富含部分。一个膜段用于富有机物部分，并将其分离成更富有机物的亚馏分和富含水的富有机物的亚馏分，而另一个膜部分对有机物贫乏的固体富含馏分从蒸馏段中分离出来，并将其分离成富含固体的亚馏分和固体贫乏的富水子馏分。

8. 发明申请

WO2013110055A1 APPARATUS AND METHODS TO HIDE POWER SIGNATURE IN CRYPTOGRAPHIC CIRCUITS 审中-公开
标题翻译：隐藏电路中功率签名的设备和方法
公开(公告)号：WO2013110055A1
公开(公告)日：2013-07-25
申请号：PCT/US2013/022501
申请日：2013-01-22
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENT JAPAN LIMITED
发明人： SEOK, Mingoo , REN, Jing-Fei , GOEL, Manish
IPC分类号： H04L9/00
CPC分类号： G06F21/558 , G06F1/26 , G06F21/755
摘要： A cryptographic device (200) reduces risk of external analysis of power consumed by an encryption circuit (206) by maintaining a substantially current draw on an external power input node (Nl) during operation. An active shunt current regulator (208) draws current to ground when not drawn by the encryption circuit (206). A low-pass filter (202) and a linear voltage regulator (204) smoothes power spikes and keeps power supply voltage constant at an input to the encryption circuit (206).
摘要翻译：加密设备（200）通过在操作期间通过维持外部功率输入节点（N1）上的基本上电流消耗来降低由加密电路（206）消耗的功率的外部分析的风险。主动分流电流调节器（208）在不被加密电路（206）拉制时将电流吸引到地。低通滤波器（202）和线性电压调节器（204）平滑功率尖峰并且在加密电路（206）的输入端保持电源电压恒定。

9. 发明申请

WO2017087950A1 METHODS AND APPARATUS TO DETECT AND CORRECT ERRORS IN DESTRUCTIVE READ NON-VOLATILE MEMORY 审中-公开
标题翻译：用于检测和校正破坏性读取非易失性存储器中的错误的方法和设备
公开(公告)号：WO2017087950A1
公开(公告)日：2017-05-26
申请号：PCT/US2016/063098
申请日：2016-11-21
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： ZHU, Yuming , GOEL, Manish , ZHANG, Sai
IPC分类号： G11C29/42
CPC分类号： G06F11/1068 , G06F11/1048 , G06F11/3037 , G06F11/3062 , G11C11/22 , G11C16/26 , G11C16/30 , G11C29/021 , G11C29/04 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C29/52 , G11C2029/0407
摘要： In described examples of methods and apparatus (102) to detect and correct errors in destructive read non-volatile memory (104), the method and apparatus (102) determine, in response to stabilizing a power supply, a status signature stored in non-volatile memory (104). In examples where the status signature is not normal, the methods and apparatus (102) decode an error correction code that is encoded in the destructive read non-volatile memory (104).
摘要翻译：在所描述的用于检测和纠正破坏性读取非易失性存储器（104）中的错误的方法和装置（102）的示例中，所述方法和装置（102）响应于稳定电源，存储在非易失性存储器（104）中的状态签名。在状态签名不正常的示例中，方法和装置（102）解码在破坏性读取非易失性存储器（104）中编码的错误校正码。

10. 发明申请

WO2015148700A1 CRC-BASED FORWARD ERROR CORRECTION CIRCUITRY AND METHOD 审中-公开
标题翻译：基于CRC的前向纠错电路和方法
公开(公告)号：WO2015148700A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/022535
申请日：2015-03-25
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： REN, Jing-fei , GOEL, Manish , ZHU, Yuming
IPC分类号： H03M13/15
CPC分类号： H03M13/09 , H04L1/0041 , H04L1/0045 , H04L1/0061 , H04L1/16
摘要： In described examples, a communication system includes digital transmitter circuitry (26) including a CRC (cyclic redundancy check) generator circuit (28) generating a first CRC code based on a message and appending the CRC code to the message a first data packet, and circuitry (26-1, 26-2, 26-3) transforming the first data packet to provide a second data packet and transmitting it. Digital receiver circuitry (120) includes circuitry (12-1, 12-2, 12-3) receiving the second data packet, a CRC verification circuit (14-1) comparing a received digital CRC code portion of the second data packet to a calculated digital CRC code portion including any introduced error to detect the existence of any error in the second data packet. The message is presented for further processing if no error is detected, and a CRC -based FEC (forward error correction) circuit (14-2) receives the message and calculated digital CRC code from the CRC verification circuit (14-1) if an error is detected, corrects the detected error, and indicates the error is uncorrectable if the correction is unsuccessful.
摘要翻译：在所描述的示例中，通信系统包括数字发射机电路（26），数字发射机电路（26）包括CRC（循环冗余校验）生成器电路（28），基于消息产生第一CRC码并将CRC码附加到消息第一数据包，以及电路（26-1,26-2,26-3）转换第一数据分组以提供第二数据分组并发送它。数字接收机电路（120）包括接收第二数据分组的电路（12-1,12-2,12-3）; CRC验证电路（14-1）将第二数据分组的接收数字CRC码部分与计算的数字CRC码部分包括任何引入的错误，以检测第二数据包中是否存在任何错误。如果没有检测到错误，则呈现用于进一步处理的消息，并且基于CRC的FEC（前向纠错）电路（14-2）从CRC验证电路（14-1）接收消息和计算的数字CRC码，如果检测到错误，纠正检测到的错误，并指示错误是不可校正的，如果校正失败。

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