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1. 发明申请

WO2008150554A3 METHOD FOR RAPID ESTIMATION OF LAYOUT-DEPENDENT THRESHOLD VOLTAGE VARIATION IN A MOSFET ARRAY 审中-公开
标题翻译： MOSFET阵列快速估计依赖于阈值电压变化的方法
公开(公告)号：WO2008150554A3
公开(公告)日：2009-12-23
申请号：PCT/US2008051343
申请日：2008-01-17
申请人： SYNOPSYS INC , MOROZ VICTOR , PRAMANIK DIPANKAR
发明人： MOROZ VICTOR , PRAMANIK DIPANKAR
IPC分类号： G06F17/50
CPC分类号： H01L21/823412 , G06F17/5036 , H01L21/823425 , H01L27/0207
摘要： An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si / STI edges on the selected area as well as channel areas and their associated gate / Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations.
摘要翻译：用于估计集成电路布局中阈值电压的布局引起的变化的自动化方法。该方法开始于在布局内选择扩散区域以进行分析的步骤。然后，系统识别所选区域的Si / STI边缘以及通道区域及其相关的栅极/ Si边缘。接下来，识别每个识别的通道区域中的阈值电压变化，这需要由于纵向方向的影响而计算阈值电压变化的进一步步骤; 计算由于横向影响引起的阈值电压变化; 并且将纵向和横向变化组合以提供整体变化。最后，通过组合来自各个通道变化的变化来确定总体变化。

2. 发明申请

WO2010123659A3 METHOD AND APPARATUS FOR PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS 审中-公开
标题翻译：用于将过渡晶体管放置在穿透硅中的方法和装置
公开(公告)号：WO2010123659A3
公开(公告)日：2011-01-13
申请号：PCT/US2010029326
申请日：2010-03-31
申请人： SYNOPSYS INC , SPROCH JAMES DAVID , MOROZ VICTOR , XU XIAOPENG , KARMARKAR ADITYA PRADEEP
发明人： SPROCH JAMES DAVID , MOROZ VICTOR , XU XIAOPENG , KARMARKAR ADITYA PRADEEP
IPC分类号： G06F17/50 , G06F17/00
CPC分类号： G06F17/5072 , G06F17/5009 , G06F17/5036 , G06F17/5068 , G06F17/5081 , G06F2217/12 , G06F2217/82 , H01L21/76898 , H01L21/823807 , H01L27/0207 , H01L29/7845 , H01L2924/0002 , Y02P90/265 , H01L2924/00
摘要： Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSVs near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.
摘要翻译：粗略地描述，本发明涉及表征，考虑或利用由晶体管附近的TSV引入的应力的方法。在表征电路时，可以考虑TSV和附近晶体管之间的物理关系。在不了解TSV和附近晶体管之间的物理关系的情况下导出的布局可以进行修改。宏单元可以包括TSV和附近晶体管，以及考虑到晶体管和TSV之间的物理关系的宏单元的仿真模型。宏单元可以包括TSV和附近的晶体管，其中一个晶体管相对于其他晶体管旋转。 IC还可以包括在TSV附近的晶体管，以将通道中的载流子迁移率改变超过先前认为限定排除区的极限。

3. 发明申请

WO2013019450A3 N-CHANNEL AND P-CHANNEL FINFET CELL ARCHITECTURE WITH INTER-BLOCK INSULATOR 审中-公开
标题翻译：具有隔离绝缘体的N沟道和P沟道FinFET单元结构
公开(公告)号：WO2013019450A3
公开(公告)日：2013-04-04
申请号：PCT/US2012047829
申请日：2012-07-23
申请人： SYNOPSYS INC , KAWA JAMIL , MOROZ VICTOR , SHERLEKAR DEEPAK
发明人： KAWA JAMIL , MOROZ VICTOR , SHERLEKAR DEEPAK
IPC分类号： H01L21/77 , H01L21/28 , H01L21/336 , H01L29/78
CPC分类号： G06F17/505 , G06F17/5068 , G06F17/5072 , G06F17/5077 , H01L23/528 , H01L27/0207 , H01L27/0886 , H01L27/0924 , H01L27/1211 , H01L2924/0002 , H01L2924/00
摘要： A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks.
摘要翻译： finFET块结构包括具有第一导电类型的第一组半导体鳍片和具有第二导电类型的第二组半导体鳍片。在第一和第二组的外部散热片之间放置一个块间绝缘体。图案化栅极导体层包括跨越第一块中的翅片集合延伸的第一多个栅极迹线，而不跨越块间绝缘体;以及第二多个栅极迹线，跨越第二块中的翅片组延伸，而不跨越块间绝缘体。栅极导体层上的图案化导体层以正交布局图案布置，并且包括布置成连接第一和第二块中的栅极迹线的块间连接器。

4. 发明申请

WO2013188410A3 N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE 审中-公开
标题翻译： N沟道和P沟道端到端FINFET单元结构
公开(公告)号：WO2013188410A3
公开(公告)日：2014-02-20
申请号：PCT/US2013045187
申请日：2013-06-11
申请人： SYNOPSYS INC , MOROZ VICTOR
发明人： MOROZ VICTOR
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/0886 , G06F17/5068 , G06F17/5072 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L27/0207 , H01L27/0924 , H01L29/0649 , H01L29/42372 , H01L29/7848
摘要： A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The ends of the fins in the first set are proximal to a first side of the inter-block isolation structure and ends of the fins in the second set are proximal to a second side of the inter-block isolation structure. A patterned gate conductor layer includes a first gate conductor extending across at least one fin in the first set of semiconductor fins, and a second gate conductor extending across at least one fin in the second set of semiconductor fins. The first and second gate conductors are connected by an inter-block conductor.
摘要翻译： finFET块结构使用端到端finFET块。具有第一导电类型的第一组半导体鳍片和具有第二导电类型的第二组半导体鳍片可以端对齐地对准。块间隔离结构分离第一和第二组中的半导体鳍片。第一组中的翅片的端部靠近块体间隔离结构的第一侧，并且第二组中的翅片的端部接近块体间隔离结构的第二侧。图案化栅极导体层包括延伸穿过第一组半导体鳍片中的至少一个翅片的第一栅极导体，以及延伸穿过第二组半导体鳍片中的至少一个翅片的第二栅极导体。第一和第二栅极导体通过块间导体连接。

5. 发明申请

WO2013016140A3 INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE AND METHODS FOR MANUFACTURING THE SAME 审中-公开
标题翻译：具有降低边缘曲线特征的集成电路装置及其制造方法
公开(公告)号：WO2013016140A3
公开(公告)日：2013-04-04
申请号：PCT/US2012047431
申请日：2012-07-19
申请人： SYNOPSYS INC , MOROZ VICTOR , BOMHOLT LARS
发明人： MOROZ VICTOR , BOMHOLT LARS
IPC分类号： H01L21/027 , H01L27/02
CPC分类号： H01L29/045 , H01L21/26506 , H01L21/30604 , H01L29/04 , H01L29/66795
摘要： A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material.
摘要翻译：描述了诸如集成电路器件的结构，其具有临界尺寸的材料线，其在基本上小于用于制造材料线的掩模元件（例如图案化的抗蚀剂元件）的分布内变化。

6. 发明申请

WO2014005078A9 SRAM LAYOUTS 审中-公开
标题翻译： SRAM缓存
公开(公告)号：WO2014005078A9
公开(公告)日：2014-02-13
申请号：PCT/US2013048692
申请日：2013-06-28
申请人： SYNOPSYS INC , LIN XI-WEI , MOROZ VICTOR
发明人： LIN XI-WEI , MOROZ VICTOR
IPC分类号： G11C11/41
CPC分类号： G06F17/5072 , G06F17/5068 , G11C11/412 , G11C11/419 , H01L21/823828 , H01L27/0207 , H01L27/1104
摘要： Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are described. The invention also involves layout files, macrocells, lithographic masks and integrated circuit devices incorporating these principles, as well as fabrication methods.
摘要翻译：大致描述了，SRAM阵列中的单元布局被重新布置，使得用于期望使用一个通道长度的灵活性的晶体管的栅电极沿着与用于灵活使用不同通道的晶体管不同的轨道形成长度是期望的。这样的重新布置不仅允许优化器件比率，而且在某些实现中也可以减小而不是增加单元面积。描述具体示例布局。本发明还涉及包含这些原理的布局文件，宏单元，光刻掩模和集成电路器件以及制造方法。

7. 发明申请

WO2013036806A3 METHODS FOR MANUFACTURING INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE 审中-公开
标题翻译：制造具有降低的边缘曲率特征的集成电路器件的方法
公开(公告)号：WO2013036806A3
公开(公告)日：2013-05-02
申请号：PCT/US2012054224
申请日：2012-09-07
申请人： SYNOPSYS INC , MOROZ VICTOR , BOMHOLT LARS
发明人： MOROZ VICTOR , BOMHOLT LARS
IPC分类号： H01L21/027 , H01L21/28
CPC分类号： H01L29/045 , G06F17/5045 , H01L21/30608 , H01L21/3065 , H01L21/308 , H01L29/0676
摘要： A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line.
摘要翻译：描述了一种结构，例如集成电路器件，其包括具有在分布内变化的临界尺寸的材料线，该分布明显小于用于蚀刻该线的掩模元件（诸如图案化的抗蚀剂元件）的分布。描述了用于处理已经使用掩模元件蚀刻的晶体相材料线的技术，其以使线的蚀刻侧壁表面变直的方式。拉直的侧壁表面不承载通过涉及形成掩模元件和蚀刻线的光刻工艺或其他图案化工艺引入的侧壁表面变化。

8. 发明申请

WO2012151209A3 METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：用于制造高密度集成电路器件的方法
公开(公告)号：WO2012151209A3
公开(公告)日：2013-03-21
申请号：PCT/US2012035997
申请日：2012-05-01
申请人： SYNOPSYS INC , MOROZ VICTOR , LIN XI-WEI
发明人： MOROZ VICTOR , LIN XI-WEI
IPC分类号： H01L21/027
CPC分类号： G06F17/5068 , H01L21/3086
摘要： An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process.
摘要翻译：描述了具有多条线的集成电路器件，其中线的宽度和相邻线之间的间距在小范围内变化，该范围独立于由于光刻工艺或其它图案化工艺引起的变化，涉及制造设备。描述了用于形成用于线路的蚀刻掩模的顺序侧壁间隔物形成工艺，其导致以交替方式布置的第一组和第二组侧壁间隔件。作为这种顺序侧壁间隔物工艺的结果，跨越多条线的线的宽度的变化以及相邻线之间的间隔取决于侧壁间隔件的尺寸的变化。这些变化与由图案化工艺引起的中间掩模元件的尺寸变化相比，分布远远小于分布，并且可以被控制。

9. 发明申请

WO2006011939A3 METHODS FOR FORMING A TRANSISTOR 审中-公开
标题翻译：形成晶体管的方法
公开(公告)号：WO2006011939A3
公开(公告)日：2006-10-19
申请号：PCT/US2005019328
申请日：2005-06-02
申请人： APPLIED MATERIALS INC , NOURI FARAN , WASHINGTON LORI D , MOROZ VICTOR
发明人： NOURI FARAN , WASHINGTON LORI D , MOROZ VICTOR
IPC分类号： H01L21/336 , H01L29/165
CPC分类号： H01L29/66636 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/7848
摘要： Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity.
摘要翻译：提供用于在衬底上形成半导体器件（例如金属氧化物晶体管）时沉积材料的方法。在一个实施例中，本发明总体上提供一种处理衬底的方法，包括：在具有第一导电性的衬底上形成栅极电介质;在栅极电介质上形成栅电极;沿栅极的横向相对侧壁形成第一对侧壁间隔体在电极的相对侧上蚀刻一对源极/漏极区定义，在源极/漏极区定义中选择性地沉积硅锗材料，以及在沉积的硅锗材料中注入掺杂剂以形成源极/漏极区域具有第二导电性。

10. 发明申请

WO2016033154A2 ARRAYS WITH COMPACT SERIES CONNECTION FOR VERTICAL NANOWIRES REALIZATIONS 审中-公开
标题翻译：具有紧凑型系列连接用于垂直纳米级实现的阵列
公开(公告)号：WO2016033154A2
公开(公告)日：2016-03-03
申请号：PCT/US2015046891
申请日：2015-08-26
申请人： SYNOPSYS INC
发明人： MOROZ VICTOR , KAWA JAMIL
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , B82Y10/00 , H01L21/823885 , H01L27/0207 , H01L27/092 , H01L29/0676 , H01L29/775
摘要： An integrated circuit design tool includes a functional cell library. An entry in the cell library comprises a specification of the cell. Entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library comprising a specification of a cell including a plurality of transistors and an interconnect. At least two transistors in the plurality are in series via at least the interconnect. The transistors and the interconnect can be vertically oriented to support vertical current through a vertical channel relative to the substrate.
摘要翻译：集成电路设计工具包括功能单元库。细胞库中的条目包括细胞的规格。细胞库中的条目包括计算机可执行语言中特定细胞的规格。所述单元库中的至少一个入口包括包括多个晶体管和互连的单元的规格。至少两个晶体管中的至少两个晶体管至少是互连的。晶体管和互连可以被垂直定向以支持相对于衬底通过垂直沟道的垂直电流。

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