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1. 发明申请

WO2005027227A1 MEMORY DEVICE AND METHOD OF ERASING THE SAME 审中-公开
标题翻译：存储器件及其擦除方法
公开(公告)号：WO2005027227A1
公开(公告)日：2005-03-24
申请号：PCT/US2004/016071
申请日：2004-05-21
申请人： SPANSION LLC , ZHENG, Wei , WU, Yun (Wayne) , SHIRAIWA, Hidehiko , RAMSBEY, Mark, T. , KAMAL, Tazrien
发明人： ZHENG, Wei , WU, Yun (Wayne) , SHIRAIWA, Hidehiko , RAMSBEY, Mark, T. , KAMAL, Tazrien
IPC分类号： H01L29/792
CPC分类号： H01L29/7923 , H01L29/7887
摘要： A charge trapping dielectric memory device (12). The memory device includes a gate electrode (34) disposed over a dielectric stack (18) that includes a dielectric charge trapping layer (30). The gate electrode has a work function of about 4.6 eV to about 5.2 eV.
摘要翻译：电荷捕获介质存储器件（12）。存储器件包括设置在包括介电电荷俘获层（30）的电介质叠层（18）之上的栅电极（34）。栅电极具有约4.6eV至约5.2eV的功函数。

2. 发明申请

WO2004079824A2 CHARGE-TRAPPING MEMORY ARRAYS RESISTANT TO DAMAGE FROM CONTACT HOLE FORMATION 审中-公开
标题翻译：充电跟踪记忆阵列抵抗接触孔形成的损伤
公开(公告)号：WO2004079824A2
公开(公告)日：2004-09-16
申请号：PCT/US2004/000502
申请日：2004-01-08
申请人： ADVANCED MICRO DEVICES, INC. , FUJITSU LIMITED , KAMAL, Tazrien , RAMSBEY, Mark, T. , SHIRAIWA, Hidehiko , CHEUNG, Fred, TK
发明人： KAMAL, Tazrien , RAMSBEY, Mark, T. , SHIRAIWA, Hidehiko , CHEUNG, Fred, TK
IPC分类号： H01L27/115
CPC分类号： H01L27/11568 , H01L27/115 , H01L2224/48247 , H01L2224/85464 , H01L2924/01012 , H01L2924/01019 , H01L2924/01021 , H01L2924/01057 , H01L2924/01087 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , Y10S257/90 , H01L2924/00
摘要： The present invention relates to a memory array (100) comprising a substrate (222) and a plurality of bitlines (224) having contacts (240) and a plurality of wordlines (201, 202) intersecting the bitlines (224). A protective spacer (234) is used to separate the bitline contacts (240) from the wordlines (201) adjacent to the bitline contacts (240) to prevent damage caused during the formation of the bitline contacts (240). The present invention also relates to a method of forming the memory array.
摘要翻译：本发明涉及一种存储器阵列（100），其包括具有触点（240）和与所述位线（224）相交的多个字线（201,202）的基板（222）和多个位线（224）。保护间隔物（234）用于将位线触点（240）与位线接触件（240）相邻的字线（201）分开，以防止在形成位线触头（240）期间造成的损坏。本发明还涉及形成存储器阵列的方法。

3. 发明申请

WO2005010984A2 PECVD SILICON-RICH OXIDE LAYER FOR REDUCED UV CHARGING 审中-公开
标题翻译： PECVD富含硅的氧化物层可减少紫外线充电
公开(公告)号：WO2005010984A2
公开(公告)日：2005-02-03
申请号：PCT/US2004/019664
申请日：2004-06-18
申请人： ADVANCED MICRO DEVICES, INC. , NGO, Minh Van , RAMSBEY, Mark, T. , KAMAL, Tazrien , GAO, Pei, Yuan
发明人： NGO, Minh Van , RAMSBEY, Mark, T. , KAMAL, Tazrien , GAO, Pei, Yuan
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L21/02164 , H01L21/02274 , H01L21/31604 , H01L21/76829 , H01L21/76834 , H01L23/552 , H01L27/115 , H01L29/66825 , H01L2924/0002 , H01L2924/00
摘要： A Si-rich silicon oxide layer (500) having reduced UV transmission is deposited by PECVD, on an interlayer dielectric (300) , prior to metallization, thereby reducing V t . Embodiments include depositing a UV opaque Si-rich silicon oxide layer (500) having an R.I. of 1.7 to 2.0.
摘要翻译：在金属化之前，通过PECVD在层间电介质（300）上沉积具有降低的UV透射率的富含Si的氧化硅层（500），由此减少V th / 。实施例包括沉积具有1.7至2.0的R.I.的UV不透明的富硅氧化硅层（500）。

4. 发明申请

WO2004073047A2 UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BIT FLASH MEMORY DEVICES IN BEOL PROCESSING 审中-公开
标题翻译：用于减少SONOS双位闪存器件在BEOL加工中紫外线诱导充电的紫外线阻挡层
公开(公告)号：WO2004073047A2
公开(公告)日：2004-08-26
申请号：PCT/US2004/000492
申请日：2004-01-08
申请人： ADVANCED MICRO DEVICES, INC. , NGO, Minh, Van , KAMAL, Tazrien , RAMSBEY, Mark, T. , HALLIYAL, Arvind , PARK, Jaeyong , CHENG, Ning , ERHARDT, Jeff, P. , SHIELDS, Jeffrey, A. , FERGUSON, Clarence , HUI, Angela, T. , HUERTAS, Robert, A. , GOTTIPATI, Tyagamohan
发明人： NGO, Minh, Van , KAMAL, Tazrien , RAMSBEY, Mark, T. , HALLIYAL, Arvind , PARK, Jaeyong , CHENG, Ning , ERHARDT, Jeff, P. , SHIELDS, Jeffrey, A. , FERGUSON, Clarence , HUI, Angela, T. , HUERTAS, Robert, A. , GOTTIPATI, Tyagamohan
IPC分类号： H01L
CPC分类号： H01L29/66833 , H01L21/28282 , H01L23/552 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a SONOS flash memory cell (24) from UV-induced charging, including fabricating a SONOS flash memory cell (24) in a semiconductor device (10, 50); and depositing over the SONOS flash memory cell (24) at least one UV-protective layer (38, 46, 48 or 52), the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device (10, 50), including a SONOS flash memory cell (24); and at least one UV-protective layer (38, 46, 48 or 52), in which the UV-protective layer comprises a substantially UV-opaque material, is provided.
摘要翻译：一种保护SONOS快闪存储单元（24）不受紫外线感应充电的方法，包括在半导体器件（10,50）中制造SONOS快闪存储单元（24）; 以及在SONOS闪存单元（24）上沉积至少一个UV保护层（38,46,48或52），所述UV保护层包括基本上UV不透明材料。包括SONOS闪存单元（24）的SONOS闪存设备（10,50）; 和至少一个UV保护层（38,46,48或52），其中UV保护层包括基本上UV不透明材料。

5. 发明申请

WO2006076625A1 MEMORY DEVICE HAVING TRAPEZOIDAL BITLINES AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：具有铁氰酸钾的存储器件及其制造方法
公开(公告)号：WO2006076625A1
公开(公告)日：2006-07-20
申请号：PCT/US2006/001318
申请日：2006-01-12
申请人： SPANSION LLC , MELIK-MARTIROSIAN, Ashot , RAMSBEY, Mark, T. , RANDOLPH, Mark, W.
发明人： MELIK-MARTIROSIAN, Ashot , RAMSBEY, Mark, T. , RANDOLPH, Mark, W.
IPC分类号： H01L29/792
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A memory device (100) and a method of fabrication are provided. The memory device (100) includes a semiconductor substrate (110) and a charge trapping dielectric stack (116, 118, 120) disposed over the semiconductor substrate (110). A gate electrode (122) is disposed over the charge trapping dielectric stack (116, 118, 120), where the gate electrode (122) electrically defines a channel (124) within a portion (114) of the semiconductor substrate (110). The memory device (100) includes a pair of bitlines (112), where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
摘要翻译：提供了一种存储器件（100）和制造方法。存储器件（100）包括设置在半导体衬底（110）上方的半导体衬底（110）和电荷俘获电介质叠层（116,118,120）。栅电极（122）设置在电荷捕获电介质堆叠（116,118,120）之上，其中栅电极（122）在半导体衬底（110）的一部分（114）内电气限定沟道（124）。存储装置（100）包括一对位线（112），其中位线具有下部分和基本上梯形的上部部分。

6. 发明申请

WO2005078791A1 POCKET IMPLANT FOR COMPLEMENTARY BIT DISTURB IMPROVEMENT AND CHARGING IMPROVEMENT OF SONOS MEMORY CELL 审中-公开
标题翻译：用于补充位冲突改进和SONOS存储单元充电改进的POCKET IMPLAN
公开(公告)号：WO2005078791A1
公开(公告)日：2005-08-25
申请号：PCT/US2004/042855
申请日：2004-12-17
申请人： ADVANCED MICRO DEVICES, INC. , LINGUNIS, Emmanuil, H. , WONG, Nga-Ching, Alan , HADDAD, Sameer , RANDOLPH, Mark, W. , RAMSBEY, Mark, T. , MELIK-MARTIROSIAN, Ashot , RUNNION, Edward, F. , HE, Yi
发明人： LINGUNIS, Emmanuil, H. , WONG, Nga-Ching, Alan , HADDAD, Sameer , RANDOLPH, Mark, W. , RAMSBEY, Mark, T. , MELIK-MARTIROSIAN, Ashot , RUNNION, Edward, F. , HE, Yi
IPC分类号： H01L21/8246
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1083 , H01L29/66833 , Y10S438/959
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer (608) is formed over a substrate (602) and a resist (614) is formed over the portion of the charge trapping dielectric layer (608). The resist (614) is patterned and a pocket implant (630) is performed at an angle to establish pocket implants (620) within the substrate (602). A bitline implant (634) is then performed to establish buried bitlines (640) within the substrate (602). The patterned resist is then removed and the remainder of the charge trapping dielectric layer (608) is formed. A wordline material (660) is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines (662) that overlie the bitlines (640). The pocket implants (620) serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.
摘要翻译：公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。最初，电荷俘获电介质层（608）的一部分形成在衬底（602）上，并且在电荷俘获电介质层（608）的部分上形成抗蚀剂（614）。对抗蚀剂（614）进行图案化，并且以一定角度执行凹穴注入（630）以在衬底（602）内建立凹穴注入（620）。然后执行位线植入（634）以在衬底（602）内建立掩埋位线（640）。然后去除图案化的抗蚀剂，并形成剩余的电荷捕获介电层（608）。字线材料（660）形成在电荷俘获电介质层的剩余部分上并被图案化以形成覆盖在位线（640）上的字线（662）。口袋植入物（620）用于缓解由半导体尺度缩小引起的互补位干扰（CBD）。因此，可以使半导体器件更小，并且可以通过本文所阐述的发明概念来实现增加的封装密度。

7. 发明申请

WO2005027210A1 MEMORY CELL STRUCTURE HAVING NITRIDE LAYER WITH REDUCED CHARGE LOSS AND METHOD FOR FABRICATING SAME 审中-公开
标题翻译：具有减少充电损失的具有氮化物层的存储单元结构及其制造方法
公开(公告)号：WO2005027210A1
公开(公告)日：2005-03-24
申请号：PCT/US2004/028329
申请日：2004-08-31
申请人： ADVANCED MICRO DEVICES, INC , KLUTH, George, Jonathan , CLARK-PHELPS, Robert, B. , JEON, Joong, S. , ZHONG, Huicai , HALLIYAL, Arvind , RAMSBEY, Mark, T. , OGLE, Robert, Bertram, Jr. , CHANG, Kuo-Tung , LI, Wenmei
发明人： KLUTH, George, Jonathan , CLARK-PHELPS, Robert, B. , JEON, Joong, S. , ZHONG, Huicai , HALLIYAL, Arvind , RAMSBEY, Mark, T. , OGLE, Robert, Bertram, Jr. , CHANG, Kuo-Tung , LI, Wenmei
IPC分类号： H01L21/28
CPC分类号： H01L21/28282 , H01L21/28176 , H01L21/28202 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： According to one embodiment, a memory cell structure comprises a semiconductor substrate (210), a first silicon oxide layer (215) situated over the semiconductor substrate, a charge storing layer (220) situated over the first silicon oxide layer, a second silicon oxide layer (225) situated over the charge storing layer, and a gate layer (230) situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer (220) comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer (220). The reduced charge loss in the charge storing layer (220) has the benefit of reducing threshold voltage shifts, prograirnming data loss, and programming capability loss in the memory device, thereby improving memory device performance.
摘要翻译：根据一个实施例，存储单元结构包括半导体衬底（210），位于半导体衬底之上的第一氧化硅层（215），位于第一氧化硅层上方的电荷存储层（220），第二氧化硅位于电荷存储层上方的层（225）和位于第二氧化硅层上方的栅极层（230）。在示例性实施例中，电荷存储层（220）包括具有降低的氢含量的氮化硅，例如在约0至0.5原子百分比的范围内。结果，降低的氢含量降低了电荷存储层（220）中的电荷损失。电荷存储层（220）中的减少的电荷损失有利于降低存储器件中的阈值电压偏移，编程数据丢失和编程能力损失，从而提高存储器件性能。

8. 发明申请

WO2005114734A1 BITLINE IMPLANT UTILIZING DUAL POLY 审中-公开
标题翻译：使用双重聚合物的双点植入
公开(公告)号：WO2005114734A1
公开(公告)日：2005-12-01
申请号：PCT/US2005/004540
申请日：2005-02-11
申请人： ADVANCED MICRO DEVICES, INC. , QIAN, Weidon , RAMSBEY, Mark, T. , YANG, Jean, Yee-Mei , HADDAD, Sameer
发明人： QIAN, Weidon , RAMSBEY, Mark, T. , YANG, Jean, Yee-Mei , HADDAD, Sameer
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , H01L27/11568
摘要： The present invention pertains to implementing a dual poly process (500) in forming a transistor based memory device (600). The process allows buried bitlines (662) to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials (670, 674) are also formed over the buried bitlines (662) to improve ( e . g ., increase) a breakdown voltage between the bitlines (662) and wordlines (678), thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process (500) also facilitates a reduction in buried bitline width (666) and thus allows bitlines (662) to be formed closer together. As a result, more devices can be "packed" within the same or a smaller area.
摘要翻译：本发明涉及在形成基于晶体管的存储器件（600）中实施双重聚合工艺（500）。该过程允许以比传统位线更少的能量和更浅的深度形成掩埋位线（662），以节省资源和空间，并且改善Vt滚降。氧化物材料（670,674）也形成在掩埋位线（662）上以改善（例如，增加）位线（662）和字线（678）之间的击穿电压，从而允许编程和擦除电荷之间的更大区分，更可靠的结果数据存储。过程（500）还有助于减少掩埋位线宽度（666），从而允许位线（662）更靠近地形成。因此，更多的设备可以在相同或较小的区域内“打包”。

9. 发明申请

WO2015095717A1 GATE FORMATION MEMORY BY PLANARIZATION 审中-公开
标题翻译：通过平面化的门控形成记忆
公开(公告)号：WO2015095717A1
公开(公告)日：2015-06-25
申请号：PCT/US2014/071524
申请日：2014-12-19
申请人： SPANSION LLC
发明人： FANG, Shenqing , CHEN, Chun , MATSUMOTO, David , RAMSBEY, Mark, T.
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L29/792 , H01L21/28282 , H01L21/32115 , H01L21/3212 , H01L21/32135 , H01L27/11568 , H01L29/42344 , H01L29/513 , H01L29/517 , H01L29/66833 , H01L29/7831
摘要： Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer and a sidewall dielectric is formed on a side of the poly layer. A second poly layer is formed over the gate structure such that a portion of the second poly layer includes a vertical portion that is in contact with the sidewall dielectric and a top portion that is in contact with the top dielectric. The top portion of the second poly layer can then be removed through, for instance, planarization.
摘要翻译：公开了半导体装置及其制造方法。这些器件通过在衬底上形成栅极结构而形成。栅极结构包括形成在衬底和第一多晶硅层之间的电荷俘获电介质。在多晶硅层上形成顶部电介质，并且在多晶硅层的一侧上形成侧壁电介质。第二多晶硅层形成在栅极结构之上，使得第二多晶硅层的一部分包括与侧壁电介质接触的垂直部分和与顶部电介质接触的顶部。然后可以通过例如平坦化来去除第二多晶硅层的顶部。

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