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1. 发明申请

WO2004079824A2 CHARGE-TRAPPING MEMORY ARRAYS RESISTANT TO DAMAGE FROM CONTACT HOLE FORMATION 审中-公开
标题翻译：充电跟踪记忆阵列抵抗接触孔形成的损伤
公开(公告)号：WO2004079824A2
公开(公告)日：2004-09-16
申请号：PCT/US2004/000502
申请日：2004-01-08
申请人： ADVANCED MICRO DEVICES, INC. , FUJITSU LIMITED , KAMAL, Tazrien , RAMSBEY, Mark, T. , SHIRAIWA, Hidehiko , CHEUNG, Fred, TK
发明人： KAMAL, Tazrien , RAMSBEY, Mark, T. , SHIRAIWA, Hidehiko , CHEUNG, Fred, TK
IPC分类号： H01L27/115
CPC分类号： H01L27/11568 , H01L27/115 , H01L2224/48247 , H01L2224/85464 , H01L2924/01012 , H01L2924/01019 , H01L2924/01021 , H01L2924/01057 , H01L2924/01087 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , Y10S257/90 , H01L2924/00
摘要： The present invention relates to a memory array (100) comprising a substrate (222) and a plurality of bitlines (224) having contacts (240) and a plurality of wordlines (201, 202) intersecting the bitlines (224). A protective spacer (234) is used to separate the bitline contacts (240) from the wordlines (201) adjacent to the bitline contacts (240) to prevent damage caused during the formation of the bitline contacts (240). The present invention also relates to a method of forming the memory array.
摘要翻译：本发明涉及一种存储器阵列（100），其包括具有触点（240）和与所述位线（224）相交的多个字线（201,202）的基板（222）和多个位线（224）。保护间隔物（234）用于将位线触点（240）与位线接触件（240）相邻的字线（201）分开，以防止在形成位线触头（240）期间造成的损坏。本发明还涉及形成存储器阵列的方法。

2. 发明申请

WO2005027227A1 MEMORY DEVICE AND METHOD OF ERASING THE SAME 审中-公开
标题翻译：存储器件及其擦除方法
公开(公告)号：WO2005027227A1
公开(公告)日：2005-03-24
申请号：PCT/US2004/016071
申请日：2004-05-21
申请人： SPANSION LLC , ZHENG, Wei , WU, Yun (Wayne) , SHIRAIWA, Hidehiko , RAMSBEY, Mark, T. , KAMAL, Tazrien
发明人： ZHENG, Wei , WU, Yun (Wayne) , SHIRAIWA, Hidehiko , RAMSBEY, Mark, T. , KAMAL, Tazrien
IPC分类号： H01L29/792
CPC分类号： H01L29/7923 , H01L29/7887
摘要： A charge trapping dielectric memory device (12). The memory device includes a gate electrode (34) disposed over a dielectric stack (18) that includes a dielectric charge trapping layer (30). The gate electrode has a work function of about 4.6 eV to about 5.2 eV.
摘要翻译：电荷捕获介质存储器件（12）。存储器件包括设置在包括介电电荷俘获层（30）的电介质叠层（18）之上的栅电极（34）。栅电极具有约4.6eV至约5.2eV的功函数。

3. 发明申请

WO2005010984A2 PECVD SILICON-RICH OXIDE LAYER FOR REDUCED UV CHARGING 审中-公开
标题翻译： PECVD富含硅的氧化物层可减少紫外线充电
公开(公告)号：WO2005010984A2
公开(公告)日：2005-02-03
申请号：PCT/US2004/019664
申请日：2004-06-18
申请人： ADVANCED MICRO DEVICES, INC. , NGO, Minh Van , RAMSBEY, Mark, T. , KAMAL, Tazrien , GAO, Pei, Yuan
发明人： NGO, Minh Van , RAMSBEY, Mark, T. , KAMAL, Tazrien , GAO, Pei, Yuan
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L21/02164 , H01L21/02274 , H01L21/31604 , H01L21/76829 , H01L21/76834 , H01L23/552 , H01L27/115 , H01L29/66825 , H01L2924/0002 , H01L2924/00
摘要： A Si-rich silicon oxide layer (500) having reduced UV transmission is deposited by PECVD, on an interlayer dielectric (300) , prior to metallization, thereby reducing V t . Embodiments include depositing a UV opaque Si-rich silicon oxide layer (500) having an R.I. of 1.7 to 2.0.
摘要翻译：在金属化之前，通过PECVD在层间电介质（300）上沉积具有降低的UV透射率的富含Si的氧化硅层（500），由此减少V th / 。实施例包括沉积具有1.7至2.0的R.I.的UV不透明的富硅氧化硅层（500）。

4. 发明申请

WO2004073047A2 UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BIT FLASH MEMORY DEVICES IN BEOL PROCESSING 审中-公开
标题翻译：用于减少SONOS双位闪存器件在BEOL加工中紫外线诱导充电的紫外线阻挡层
公开(公告)号：WO2004073047A2
公开(公告)日：2004-08-26
申请号：PCT/US2004/000492
申请日：2004-01-08
申请人： ADVANCED MICRO DEVICES, INC. , NGO, Minh, Van , KAMAL, Tazrien , RAMSBEY, Mark, T. , HALLIYAL, Arvind , PARK, Jaeyong , CHENG, Ning , ERHARDT, Jeff, P. , SHIELDS, Jeffrey, A. , FERGUSON, Clarence , HUI, Angela, T. , HUERTAS, Robert, A. , GOTTIPATI, Tyagamohan
发明人： NGO, Minh, Van , KAMAL, Tazrien , RAMSBEY, Mark, T. , HALLIYAL, Arvind , PARK, Jaeyong , CHENG, Ning , ERHARDT, Jeff, P. , SHIELDS, Jeffrey, A. , FERGUSON, Clarence , HUI, Angela, T. , HUERTAS, Robert, A. , GOTTIPATI, Tyagamohan
IPC分类号： H01L
CPC分类号： H01L29/66833 , H01L21/28282 , H01L23/552 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a SONOS flash memory cell (24) from UV-induced charging, including fabricating a SONOS flash memory cell (24) in a semiconductor device (10, 50); and depositing over the SONOS flash memory cell (24) at least one UV-protective layer (38, 46, 48 or 52), the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device (10, 50), including a SONOS flash memory cell (24); and at least one UV-protective layer (38, 46, 48 or 52), in which the UV-protective layer comprises a substantially UV-opaque material, is provided.
摘要翻译：一种保护SONOS快闪存储单元（24）不受紫外线感应充电的方法，包括在半导体器件（10,50）中制造SONOS快闪存储单元（24）; 以及在SONOS闪存单元（24）上沉积至少一个UV保护层（38,46,48或52），所述UV保护层包括基本上UV不透明材料。包括SONOS闪存单元（24）的SONOS闪存设备（10,50）; 和至少一个UV保护层（38,46,48或52），其中UV保护层包括基本上UV不透明材料。

5. 发明申请

WO2003088353A1 MEMORY MANUFACTURING PROCESS WITH BITLINE ISOLATION 审中-公开
标题翻译：具有分离分离的记忆制造工艺
公开(公告)号：WO2003088353A1
公开(公告)日：2003-10-23
申请号：PCT/US2003/004461
申请日：2003-02-14
申请人： ADVANCED MICRO DEVICES, INC. , FUJITSU LIMITED
发明人： RAMSBEY, Mark, T. , KAMAL, Tazrien , YANG, Jean, Y. , LINGUNIS, Emmanuil , SHIRAIWA, Hidehiko , SUN, Yu
IPC分类号： H01L21/8246
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method of manufacturing an integrated circuit is provided with a semiconductor substrate (506) having a core region (502) and a periphery region (504). A charge-trapping dielectric layer (510) is deposited in the core region (502), and a gate dielectric layer (522) is deposited in the periphery region (504). Bitlines (518) are formed in the semiconductor substrate (506) in the core region (502) and not in the periphery region (504). A wordline-gate layer (524) is formed and implanted with dopant in the core region (502) and not in the periphery region (504). A wordline (528) and gate (530) are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate (506) around the gate (530), and the gate (530) is implanted with a gate doping implantation in the periphery region (504) and not in the core region (502).
摘要翻译：集成电路的制造方法具有芯部区域（502）和外围区域（504）的半导体基板（506）。在芯区域（502）中沉积电荷捕获介电层（510），并且在周边区域（504）中沉积栅介质层（522）。位线（518）形成在芯区域（502）中的半导体衬底（506）中，而不是在周边区域（504）中。在芯区域（502）中而不是周边区域（504）中形成并注入掺杂剂的字线栅层（524）。形成字线（528）和门（530）。在半导体衬底（506）中围绕栅极（530）注入掺杂剂源极/漏极结，栅极（530）在外围区域（504）而不是在核心区域（502）中注入栅极掺杂注入）。

6. 发明申请

WO2003083916A1 MEMORY WORDLINE HARD MASK EXTENSION 审中-公开
公开(公告)号：WO2003083916A1
公开(公告)日：2003-10-09
申请号：PCT/US2003/001851
申请日：2003-01-21
申请人： ADVANCED MICRO DEVICES, INC. , FUJITSU LIMITED
发明人： KAMAL, Tazrien , NGO, Minh, Van , RAMSBEY, Mark, T. , SHIELDS, Jeffrey, A. , YANG, Jean, Y. , LINGUNIS, Emmanuil , SHIRAIWA, Hidehiko , HUI, Angela, T.
IPC分类号： H01L21/28
CPC分类号： H01L27/11568 , H01L27/115
摘要： A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines (525) (526) formed by using the hard mask extensions (524). A charge-trapping dielectric material (504) is deposited over a semiconductor substrate (501) and first and second bitlines (512) are formed therein. A wordline material (515) and a hard mask material (515) are deposited over the wordline material (515). A photoresist material (518) is deposited over the hard mask material (515) and is processed to form a patterned photoresist material (518). The hard mask material (515) is processed using the patterned photoresist material (518) to form a patterned hard mask material (519). The patterned photoresist is then removed. A hard mask extension material (524) is deposited over the wordline material (515) and is processed to form a hard mask extension (524). The wordline material (515) is processed using the patterned hard mask material (519) and the hard mask extension (524) to form a wordline (525), and the patterned hard mask material (519) and the hard mask extension (524) are then removed.
摘要翻译：提供一种用于通过使用硬掩模延伸部（524）形成的具有紧密间隔的字线（525）（526）的集成电路存储器的制造方法。电荷俘获电介质材料（504）沉积在半导体衬底（501）上，并且在其中形成第一和第二位线（512）。字线材料（515）和硬掩模材料（515）沉积在字线材料（515）上。光致抗蚀剂材料（518）沉积在硬掩模材料（515）上并被处理以形成图案化的光致抗蚀剂材料（518）。使用图案化的光致抗蚀剂材料（518）处理硬掩模材料（515）以形成图案化的硬掩模材料（519）。然后去除图案化的光致抗蚀剂。硬掩模延伸材料（524）沉积在字线材料（515）上并被处理以形成硬掩模延伸部（524）。使用图案化的硬掩模材料（519）和硬掩模延伸部（524）来加工字线材料（515）以形成字线（525），并且图案化的硬掩模材料（519）和硬掩模延伸部（524）然后被删除。

7. 发明申请

WO2003003451A1 ISOLATION OF SONOS DEVICES 审中-公开
标题翻译： SONOS设备的隔离
公开(公告)号：WO2003003451A1
公开(公告)日：2003-01-09
申请号：PCT/US2001/049047
申请日：2001-12-14
申请人： ADVANCED MICRO DEVICES, INC. , FUJITSU LIMITED
发明人： YANG, Jean, Yee-Mei , RAMSBEY, Mark, T. , LINGUNIS, Emmanuil, Manos , WU, Yider , KAMAL, Tazrien , HE, Yi , HSIA, Edward , SHIRAIWA, Hidehiko
IPC分类号： H01L21/8246
CPC分类号： H01L21/2652 , H01L21/2658 , H01L27/11568 , H01L29/66833
摘要： One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric, if present; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric, if present; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, or forming additional material over the third layer of the charge trapping dielectric.
摘要翻译：本发明的一个方面涉及一种形成SONOS型非易失性半导体存储器件的方法，包括在半导体衬底上形成电荷俘获电介质的第一层; 在所述半导体衬底上的所述电荷俘获电介质的所述第一层上形成所述电荷俘获电介质的第二层; 可选地至少部分地在所述半导体衬底上的所述电荷俘获电介质的所述第二层上形成所述电荷俘获电介质的第三层; 任选地去除电荷捕获电介质的第三层（如果存在）在电荷俘获电介质上形成源极/漏极掩模; 将源极/漏极注入物通过电荷俘获电介质注入到半导体衬底中; 任选地去除电荷捕获电介质的第三层（如果存在）以及在半导体衬底上的电荷俘获电介质的第二层上形成电荷俘获电介质的第三层之一，在半导体衬底上的电荷俘获电介质的第二层上重整第三层电荷俘获电介质，或在电荷俘获电介质的第三层上形成附加材料。

8. 发明申请

WO2003079446A1 HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS 审中-公开
标题翻译：用于存储器件的硬掩模工艺，不含任何短路
公开(公告)号：WO2003079446A1
公开(公告)日：2003-09-25
申请号：PCT/US2003/001855
申请日：2003-01-21
申请人： ADVANCED MICRO DEVICES, INC. , FUJITSU LIMITED
发明人： YANG, Jean, Y. , RAMSBEY, Mark, T. , SHIRAIWA, Hidehiko , WU, Yider , LINGUNIS, Emmanuil , KAMAL, Tazrien
IPC分类号： H01L27/112
CPC分类号： H01L27/11568 , H01L27/115
摘要： A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate [102] [602] and depositing a charge-trapping dielectric layer [504] [606]. First and second bitlines [512] [608] are implanted and a wordline layer [515] is deposited [610]. A hard mask layer [516] is deposited over the wordline layer [515] [612]. The hard mask layer [516] is of a material formulated for removal without damaging the charge-trapping dielectric layer [504]. A photoresist [518] is deposited over the wordline layer [515] and used to form a hard mask [519] [618]. The photoresist [518] is removed [620]. The wordline layer [515] is processed using the hard mask [519] to form a wordline [525-528].
摘要翻译：用于MirrorBit闪存的制造方法包括提供半导体衬底[102]和沉积电荷俘获介电层[504] [606]。植入第一和第二位线[512] [608]，并且存储字线层[515] [610]。硬掩模层[516]沉积在字线层[515] [612]上。硬掩模层[516]是配制用于去除而不损坏电荷捕获电介质层的材料[504]。光刻胶[518]沉积在字线层[515]上并用于形成硬掩模[618]。 [620]去除光致抗蚀剂[620]。使用硬掩模[519]处理字线层[515]以形成字线[525-528]。

9. 发明申请

WO2004066396A1 MEMORY DEVICE HAVING A P+ GATE AND THIN BOTTOM OXIDE AND METHOD OF ERASING SAME 审中-公开
标题翻译：具有P +和低级氧化钛的存储器件及其擦除方法
公开(公告)号：WO2004066396A1
公开(公告)日：2004-08-05
申请号：PCT/US2003/030000
申请日：2003-09-24
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ZHENG, Wei , CHANG, Chi , KAMAL, Tazrien
IPC分类号： H01L29/792
CPC分类号： H01L29/7923 , H01L29/7887
摘要： A non-volatile memory device (10) includes a semiconductor substrate (12) and an N-type source (14) and drain (16) within the substrate (12). An oxide-nitride-oxide (ONO) stack (26, 28, 30) is formed over the substrate (12). The ONO stack (26, 28, 30) includes a thin bottom oxide layer (26). A P + polysilicon gate electrode (32) is formed over the ONO stack (26, 28, 30). The memory device (10) is operative to perform a channel erase operation in which a pair of charge storing cells (36, 38) within the nitride layer (28) are erased simultaneously.
摘要翻译：非易失性存储器件（10）包括在衬底（12）内的半导体衬底（12）和N型源极（14）和漏极（16）。在衬底（12）上形成氧化物 - 氧化物 - 氧化物（ONO）堆叠（26,28,30）。 ONO堆叠（26,28,30）包括薄的底部氧化物层（26）。在ONO堆叠（26,28,30）上形成P +多晶硅栅电极（32）。存储器件（10）可操作以执行信道擦除操作，其中氮化物层（28）内的一对电荷存储单元（36,38）同时被擦除。

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