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1. 发明申请

WO1997033317A1 CHIP CARD WITH ESD-PROTECTION 审中-公开
标题翻译：具有ESD保护芯片卡
公开(公告)号：WO1997033317A1
公开(公告)日：1997-09-12
申请号：PCT/DE1997000368
申请日：1997-02-28
申请人： SIEMENS AKTIENGESELLSCHAFT , VON BASSE, Paul-Werner , THEWES, Roland , BOLLU, Michael , SCHMITT-LANDSIEDEL, Doris
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L23/498
CPC分类号： H01L23/49855 , G06K19/077 , H01L23/5388 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： The invention concerns a chip card made of a material which is at least partly electrically conductive, which makes it possible for a potential difference on the chip card to be diminished so rapidly that a chip integrated in the card is not damaged. For the same purpose, the top side of the chip card can be coated with a thin, electrically conductive film which is connected to conductive contacts of a chip by means of vertical conductive connections.
摘要翻译：包括一个至少部分导电的材料芯片卡与施加到芯片卡的电势差的电压被迅速降解，使得在卡的集成芯片不被损坏实现。其可以应用于用于在芯片卡，它是由一个芯片的导电端子垂直导电连接相连接的导电性薄膜的顶部上的相同的目的。

2. 发明申请

WO1997026656A1 ELECTRONIC CIRCUIT 审中-公开
标题翻译：电子电路
公开(公告)号：WO1997026656A1
公开(公告)日：1997-07-24
申请号：PCT/DE1997000071
申请日：1997-01-16
申请人： SIEMENS AKTIENGESELLSCHAFT , VON BASSE, Paul-Werner , THEWES, Roland , SCHMITT-LANDSIEDEL, Doris , BOLLU, Michael
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G11C07/06
CPC分类号： G01R27/02
摘要： The invention concerns an electronic circuit comprising an inverter and a further transistor (M3) of which the gate connection is connected to the inverter output and of which the source and drain connections are connected between the input of the inverter (PL) and a connection of the supply voltage (VDD) such that a feedback loop is produced. When the input voltage drops from a maximum value as a result of low resistance at the test lead when a given voltage value is attained, the feedback loop allows the output voltage to jump to an extreme value such that the current flowing through the circuit first increases to a maximum and is interrupted abruptly when a maximum current intensity is reached. A fourth transistor (M4) between the further transistor (M3) and the connection to the supply voltage is provided in order to adapt the circuit to different conditions by applying a control voltage (VS) to the gate of this transistor. This circuit can, for example, be used to read semiconductor memories.
摘要翻译：连接在逆变器和另外的晶体管（M3），其栅极端子连接到逆变器和逆变器（PL）的输入之间的源极和漏极端子的输出的电子电路和电源电压的端子（VDD）是，使得反馈实现，其可以跳输出电压极值当输入电压从最大值下降的测试线的低电阻的结果，当一定的电压值，使得电流流过电路第一增加到最大并达到最大电流时突然中断。该另一个晶体管（M3）和到电源的连接之间的第四晶体管（M4）被施加控制电压（VS）到这个晶体管的栅极，以适应电路以不同的条件规定。该电路可以是例如被用于读出的半导体存储器。

3. 发明申请

WO1997010600A1 DEVICE FOR SKIP ADDRESSING CERTAIN LINES IN A SERIALLY OPERATING DIGITAL STORE 审中-公开
标题翻译： DEVICE对于串行数字工作记忆的某些行跳的方式满足
公开(公告)号：WO1997010600A1
公开(公告)日：1997-03-20
申请号：PCT/DE1996001511
申请日：1996-08-13
申请人： SIEMENS AKTIENGESELLSCHAFT , BOLLU, Michael , VON BASSE, Paul-Werner , THEWES, Roland , SCHMITT-LANDSIEDEL, Doris
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G11C08/04
CPC分类号： G11C8/04
摘要： To skip any distances, a device for skip addressing bit or word lines (11 to 1N) of a serially operating store has two open control loops (2, 3) allocated to the lines together and one linkage component (41 to 4N) per line, where each linkage component is connected precisely to one pair of outputs of the two open control loops and one line is precisely addressed when the bit "1" is applied to said pair of outputs.
摘要翻译：为了实现任何跳跃距离包括用于跳跃点的装置寻址串联操作存储器的位或字线（11〜1N）的两行一起相关联的控制链（2，3）和每行相应的连接元件（41到4N），与每个连杆部件正好与一个对的两个控制链的输出端连接，并且当施加到该对输出，二进制“1”的线随后被寻址准确。

4. 发明申请

WO1998012812A1 STEEP EDGE TIME-DELAY RELAY 审中-公开
标题翻译：具有陡峭边沿的延迟水平
公开(公告)号：WO1998012812A1
公开(公告)日：1998-03-26
申请号：PCT/DE1997001802
申请日：1997-08-20
申请人： SIEMENS AKTIENGESELLSCHAFT , VON BASSE, Paul-Werner , THEWES, Roland , BOLLU, Michael , SCHMITT-LANDSIEDEL, Doris
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H03K05/13
CPC分类号： H03K5/133
摘要： The invention relates to a time-delay relay from an inverter with high-resistance transistors (M1,M2) and an additional series-connected inverter with low-resistance transistors (M3 and M4) wherein MOS capacitors are provided betwen the gates of the transistors of the low-resistance inverter and the time-delay relay output (D) . The circuit enables time-delay relays to be made using a relatively small number of components.
摘要翻译：本申请的主题涉及与高电阻晶体管（M1，M2）的逆变器构成的并且串联连接反相器具有低晶体管（M3和M4），一个延迟电路，其中所述低逆变器的晶体管的栅极和所述延迟级MOS的输出（D）之间提供能力。该电路延迟级可与和上部件相对较低的费用陡峭边缘来实现。

5. 发明申请

WO1996025741A2 MULTI-VALUED READ-ONLY STORAGE LOCATION WITH IMPROVED SIGNAL-TO-NOISE RATIO 审中-公开
标题翻译：具有改进的SNR价FESTIVAL MEMORY CELL
公开(公告)号：WO1996025741A2
公开(公告)日：1996-08-22
申请号：PCT/DE1996000168
申请日：1996-02-05
申请人： SIEMENS AKTIENGESELLSCHAFT , SCHMITT-LANDSIEDEL, Doris , THEWES, Roland , BOLLU, Michael , BASSE, Paul-Werner
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G11C11/56
CPC分类号： H01L29/7923 , G11C11/56 , G11C11/5671 , G11C11/5692 , G11C16/0475
摘要： The invention concerns a multi-valued read-only storage location which is constructed symmetrically for storing a first or second state (M, M''') and asymmetrically for storing at least a third state (M', M"). The advantage thereof is above all that the storage capacity is doubled without notably increasing expenditure and without impairing the signal-to-noise ratio with respect to conventional storage locations. The invention is suitable for electrically programmable and mask-programmable read-only memories, in particular for those used in low-voltage technology.
摘要翻译：本申请的主题涉及一种多值只读存储单元用于存储第一或第二状态（M，M“”“）对称地和用于至少存储一个第三状态（M”，M“）被不对称地构成。在这种方式实现的优点在于这样的事实如果没有附加的显著努力没有信噪比超过传统存储单元劣化获得的存储容量加倍。本申请适合于电可编程和掩膜可编程只读存储器，特别是那些在低压技术。

6. 发明申请

WO1998027593A1 ARRANGEMENT FOR CONTROLLING PARALLEL LINES IN A STORAGE CELL ARRANGEMENT 审中-公开
标题翻译：布置，对于控制存储器单元装置平行线
公开(公告)号：WO1998027593A1
公开(公告)日：1998-06-25
申请号：PCT/DE1997002654
申请日：1997-11-12
申请人： SIEMENS AKTIENGESELLSCHAFT , HOFMANN, Franz , WILLER, Josef , REISINGER, Hans , VON BASSE, Paul, Werner , KRAUTSCHNEIDER, Wolfgang
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L27/112
CPC分类号： H01L27/0207 , H01L27/1126 , H01L27/11293 , H01L27/11803
摘要： In order to control parallel lines, for example bit lines (BLn) of a storage cell arrangement with doped regions in a semiconductor substrate, several lines (BLn) are electrically connected to one another and to a common node (K). Several selection lines (ALn) are provided transversely to the lines (BLn). At their crossing points are arranged MOS-transistors (M1, M2) mounted in series along one of the lines (BLn) and whose gate electrodes are formed by the corresponding selection line (ALn). At least one MOS-transistor (M1) in each of the parallel lines (BL1) has a higher operation voltage than the others.
摘要翻译：用于驱动的平行线，例如，位布置在包括掺杂区的半导体衬底的存储单元阵列的行（BLn的），多条线（BLn的）电连接在一起，并且至公共节点（K）。横向于所述线（BLn的）提供了多个选择线（ALN）。 MOS晶体管是在交叉点处（M1，M2）被布置，其中（BLn的）串联连接沿着线和栅电极中的一个通过相应的选择线（ALN）形成。至少一个MOS晶体管（M1）中的每个平行线的（BL1）具有比其他更高的阈值电压。

7. 发明申请

WO1998027594A1 MEMORY CELL ARRANGEMENT AND PROCESS FOR MANUFACTURING THE SAME 审中-公开
标题翻译：存储器单元装置和方法及其
公开(公告)号：WO1998027594A1
公开(公告)日：1998-06-25
申请号：PCT/DE1997002730
申请日：1997-11-20
申请人： SIEMENS AKTIENGESELLSCHAFT , HOFMANN, Franz , WILLER, Josef , REISINGER, Hans , VON BASSE, Paul-Werner , KRAUTSCHNEIDER, Wolfgang
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L27/115
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L27/11517
摘要： Several mutually insulated memory cell lines arranged in a semiconductor substrate (21) include each a first doped region (D1') and a second doped region (D2') between which are arranged a gate dielectric (29, 32) which contains a material with charge carriers capturing points and several gate electrodes (WL1', WL2'). The distance between adjacent gate electrodes (WL1', WL2') is smaller than the dimensions of the gate electrodes (WL1', WL2'). Information is stored by introducing charge carriers into the gate dielectric (29, 32). The gate electrodes (WL1', WL2') are preferably produced by a spacer technique.
摘要翻译：在半导体基板（21）上设置有多个互相绝缘的收容单元列，每个具有包括具有材料的载流子的第一掺杂区域（D1“）和第二掺杂区（D2”），在它们之间的栅极电介质（29，32）含有粘附位点，以及多个栅电极（WL1”，WL2' ）被布置。相邻的栅电极（WL1”，WL2‘）之间的距离比栅电极的尺寸更小（WL1’，WL2' ）。的信息是由引入的电荷载流子进入Gatedieletrikum（29，32）被存储。栅电极（WL1”，WL2' ）优选地通过间隔技术制备。

8. 发明申请

WO1998027586A1 METHOD FOR MANUFACTURING A MEMORY CELL CONFIGURATION 审中-公开
标题翻译：一种用于生产存储器单元装置
公开(公告)号：WO1998027586A1
公开(公告)日：1998-06-25
申请号：PCT/DE1997002549
申请日：1997-11-04
申请人： SIEMENS AKTIENGESELLSCHAFT , HOFMANN, Franz , WILLER, Josef , REISINGER, Hans , KRAUTSCHNEIDER, Wolfgang , VON BASSE, Paul-Werner
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L21/8246
CPC分类号： H01L27/112
摘要： In order to manufacture a memory cell configuration comprising a first series of memory cells including a vertical MOS transistor and a second series of memory cells without MOS transistor, the memory cells being arranged along the opposing flanks of strip-shaped pits, tiled memory cells are built one after the other along said pits (5). The spacing between the memory cells is determined according to a spacer technology enabling to meet the space need per memory cell, i.e. 1F , where F represents the minimum structural quantity specific to said technology.
摘要翻译：一种用于制造存储单元阵列，其包括具有垂直MOS晶体管第一存储单元，和第二存储单元，其没有晶体管MOS，所述存储单元被沿着带状沟槽的相对边缘布置是沿着连续相邻的存储单元之间的沟槽（5）产生的。相邻存储单元之间的距离是特别通过间隔技术确定。因此，每1F <2>的存储器单元的空间需求，可以实现，其中F是该技术的最小特征尺寸。

9. 发明申请

WO1997023905A3 METHOD OF PRODUCING A NEURON MOS TRANSISTOR ON THE BASIS OF A CMOS PROCESS 审中-公开
公开(公告)号：WO1997023905A3
公开(公告)日：1997-07-03
申请号：PCT/DE1996002286
申请日：1996-11-28
申请人： SIEMENS AKTIENGESELLSCHAFT , WEBER, Werner , THEWES, Roland
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： H01L21/8234

10. 发明申请

WO1996042050A1 CIRCUIT FOR COMPARING TWO ELECTRICAL QUANTITIES PROVIDED BY A FIRST NEURON MOS FIELD EFFECT TRANSISTOR AND A REFERENCE SOURCE 审中-公开
标题翻译：电路为两个电动尺寸从第一神经元MOS场效应晶体管和参考源比较提供
公开(公告)号：WO1996042050A1
公开(公告)日：1996-12-27
申请号：PCT/DE1996000972
申请日：1996-06-03
申请人： SIEMENS AKTIENGESELLSCHAFT , THEWES, Roland , PRANGE, Stefan , WOHLRAB, Erdmute , WEBER, Werner
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G06F07/52
CPC分类号： G06F7/53 , G06F2207/4826 , H03K5/2481 , H03K5/249
摘要： The invention relates to a circuit which compares a quantity supplied by a first neuron MOS field effect transistor (M1) with a reference value provided by a reference source (R). To this end there is a current mirror (SP) facilitating a comparison between a second current (I2) supplied by a reference transistor (R) and a first current (I1) supplied by the first neuron MOS field effect transistor (M1). The assessment circuit is activated or decoupled by a first switch unit (S1) and a second switch unit (S2). This ensures that no current flows in the evaluation circuit in the inoperative position. The result of comparison is applied to an inverter stage (IS). As the inverter stage (IS) is decoupled from the evaluation circuit by the first switch unit (S1), there is never an undefined level at the inverter stage (IS). Advantage can be taken of this during data processing in subsequent stages.
摘要翻译：本发明涉及一种电路装置，与参考可变（R）提供的第一神经元MOS场效应晶体管（M1）中的一个的大小是由参考源提供的。为了这个目的，一个电流镜（SP）被提供，其被供给的来自参考晶体管（R）的第二电流（I 2）与所述第一神经元MOS场效应晶体管（M1）的第一电流（I1）中的一个提供的允许的比较。通过第一开关单元（S1）和第二开关单元（S2）被激活时，所述评估电路或断开。这确保了没有电流在评估电路流动处于静止状态。比较结果被施加到逆变器级（IS）。因为逆变器级（IS）通过所述第一开关单元（S1）从所述评估电路去耦，在逆变器级（IS）是从来没有在不确定电平的输出（AIS）。这可以被用来在后续阶段进一步的数据处理来获益。

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