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1. 发明申请

WO2012009068A1 FRDY PULL -UP RESISTOR ACTIVATION 审中-公开
标题翻译： FRDY PULLUP电阻启动
公开(公告)号：WO2012009068A1
公开(公告)日：2012-01-19
申请号：PCT/US2011/039421
申请日：2011-06-07
申请人： SANDISK TECHNOLOGIES INC. , CHENG, Steven, S. , HWANG, Peter , CHANG, Annie, C.
发明人： CHENG, Steven, S. , HWANG, Peter , CHANG, Annie, C.
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4239 , G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： A method and apparatus for reducing power consumption during an operation in a non-volatile storage device is disclosed. A non-volatile storage device controller that is in communication with a non-volatile memory in the non-volatile storage device receives a characteristic corresponding to a time duration required for the non-volatile memory to complete an operation. The controller disables a circuit that indicates when an operation by the non-volatile memory is complete. The controller then initiates the operation in the non-volatile memory, and maintains the circuit in a disabled state for a first predetermined time that is a portion of the time duration. The controller enables the circuit upon expiration of the first predetermined time and prior to the completion of the operation. The controller receives an indication of the completion of the operation via the circuit.
摘要翻译：公开了一种用于在非易失性存储装置中的操作期间降低功耗的方法和装置。与非易失性存储设备中的非易失性存储器通信的非易失性存储设备控制器接收与非易失性存储器完成操作所需的持续时间相对应的特性。控制器禁用指示非易失性存储器的操作何时完成的电路。然后，控制器在非易失性存储器中启动操作，并且将电路保持在禁用状态，作为持续时间的一部分的第一预定时间。控制器在第一预定时间到期并且在完成操作之前启用该电路。控制器通过电路接收完成操作的指示。

2. 发明申请

WO2011034784A1 NONVOLATILE MEMORY CONTROLLER WITH SCALABLE PIPELINED ERROR CORRECTION 审中-公开
标题翻译：非易失性存储器控制器，具有可扩展的管道错误校正
公开(公告)号：WO2011034784A1
公开(公告)日：2011-03-24
申请号：PCT/US2010/048371
申请日：2010-09-10
申请人： SANDISK CORPORATION , CHENG, Steven, S. , GUTTA, Aruna
发明人： CHENG, Steven, S. , GUTTA, Aruna
IPC分类号： G06F11/10
CPC分类号： G06F11/1044
摘要： A nonvolatile memory system includes a memory controller in communication with multiple memory dies through multiple memory interfaces. Multiple ECC blocks are provided to decode data from the multiple memory interfaces. ECC blocks are provided with a clock signal that may have a frequency that is lower than another clock signal that is provided to a host interface.
摘要翻译：非易失性存储器系统包括通过多个存储器接口与多个存储器管芯通信的存储器控制器。提供多个ECC块来解码来自多个存储器接口的数据。 ECC块被提供有可能具有低于提供给主机接口的另一个时钟信号的频率的时钟信号。

3. 发明申请

WO2011139743A1 PHASED NAND POWER-ON RESET 审中-公开
标题翻译：复位NAND上电复位
公开(公告)号：WO2011139743A1
公开(公告)日：2011-11-10
申请号：PCT/US2011/034078
申请日：2011-04-27
申请人： SANDISK CORPORATION , CHENG, Steven, S. , EA, Dennis , HUANG, Jianmin , MAK, Alexander, Kwok-tung , MOOGAT, Farookh
发明人： CHENG, Steven, S. , EA, Dennis , HUANG, Jianmin , MAK, Alexander, Kwok-tung , MOOGAT, Farookh
IPC分类号： G06F1/24
CPC分类号： G06F1/24
摘要： A method and system for phasing power-intensive operations is disclosed. A non-volatile storage device controller detects a power reset. The controller is in communication with non- volatile memories in the non- volatile storage device. In response to detecting a power reset, the controller determines a current consumption necessary to reset the non-volatile memories in the non-volatile storage device. The controller simultaneously resets all of the non-volatile memories when the determined current consumption is less than a current consumption threshold. If the determined current consumption is greater than the current consumption threshold, the controller resets a first subset of the plurality of non- volatile memories, and after a predetermined delay, resets a second subset of the non-volatile memories. Therefore, a power-intensive operation may be performed without exceeding a current consumption threshold by dividing the operation into a sequence of steps that do not exceed the threshold.
摘要翻译：公开了一种用于阶段性强力密集型操作的方法和系统。非易失性存储设备控制器检测电源复位。控制器与非易失性存储设备中的非易失性存储器通信。响应于检测到电源复位，控制器确定复位非易失性存储设备中的非易失性存储器所需的电流消耗。当确定的电流消耗小于电流消耗阈值时，控制器同时复位所有非易失性存储器。如果确定的电流消耗大于当前消耗阈值，则控制器复位多个非易失性存储器的第一子集，并且在预定延迟之后，复位非易失性存储器的第二子集。因此，通过将操作划分成不超过阈值的一系列步骤，可以不超过电流消耗阈值来执行功率密集型操作。

4. 发明申请

WO2009088920A1 SYSTEM, METHOD AND MEMORY DEVICE PROVIDING DATA SCRAMBLING COMPATIBLE WITH ON-CHIP COPY OPERATION 审中-公开
标题翻译：提供与片上复制操作兼容的数据扫描的系统，方法和存储器件
公开(公告)号：WO2009088920A1
公开(公告)日：2009-07-16
申请号：PCT/US2008/088625
申请日：2008-12-31
申请人： SANDISK IL LTD. , LIN, Jason, T. , CHENG, Steven, S. , TRAISTER, Shai
发明人： LIN, Jason, T. , CHENG, Steven, S. , TRAISTER, Shai
IPC分类号： G11C16/34 , G11C16/06 , G11C16/08
CPC分类号： G11B20/0021 , G06F12/0246 , G06F12/1408 , G06F21/72 , G06F21/725 , G06F21/79 , G06F2212/1032 , G11C7/1006 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： Data scrambling techniques implemented externally to a flash memory device are disclosed which can be used in concert with flash memory on-chip copy functionality operating internally to the flash device, thus supporting high performance copying operations. All the data stored in the flash may be scrambled, including headers and control structures. Robust file system operation may be achieved, including the capability to tolerate a power loss at any time, and yet be able to relocate data internally within the flash without having to de-scramble and then re-scramble the data. An exemplary hardware based solution has little or no impact on overall system performance, and may be implemented at very low incremental cost to increase overall system reliability. The data scrambling technique preferably uses a logical address, such as logical block address or logical page address, rather than a physical address, to determine a seed scrambling key.
摘要翻译：公开了在闪速存储器件外部实现的数据加扰技术，其可以与在闪存器件内部操作的闪存片上复制功能一起使用，从而支持高性能复制操作。存储在闪存中的所有数据可能被加扰，包括报头和控制结构。可以实现强大的文件系统操作，包括在任何时候容忍功率损耗的能力，并且还能够在闪存内部重新定位数据，而不必去除数据，然后重新加扰数据。基于硬件的示例性解决方案对整个系统性能几乎没有或没有影响，并且可以以非常低的增量成本实现，以提高整体系统的可靠性。数据加扰技术优选地使用诸如逻辑块地址或逻辑页地址的逻辑地址而不是物理地址来确定种子加密密钥。

5. 发明申请

WO2009042554A1 NONVOLATILE MEMORY WITH SELF RECOVERY 审中-公开
标题翻译：具有自我恢复功能的非易失性存储器
公开(公告)号：WO2009042554A1
公开(公告)日：2009-04-02
申请号：PCT/US2008/077267
申请日：2008-09-22
申请人： SANDISK CORPORATION , CHENG, Steven, S.
发明人： CHENG, Steven, S.
IPC分类号： G11C29/00 , G06F11/10 , G06F11/20 , G06F11/16
CPC分类号： G06F11/1666 , G06F11/20 , G11C29/74 , G11C29/765
摘要： A nonvolatile memory array includes two or more devices, each device containing data that is scrambled using a different scrambling scheme. When the same data is provided and stored in both devices, different data patterns occur in each device, so that if one of the patterns causes data pattern induced errors, the original data can be recreated from another copy that does not share the same data pattern.
摘要翻译：非易失性存储器阵列包括两个或更多个器件，每个器件包含使用不同的加扰方案加扰的数据。当相同的数据被提供并存储在两个设备中时，在每个设备中出现不同的数据模式，使得如果其中一个模式导致数据模式引起的错误，则可以从不共享相同数据模式的另一个副本重新创建原始数据。

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