专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2006101500A1 NON-VOLATILE MEMORY AND METHOD WITH POWER-SAVING READ AND PROGRAM-VERIFY OPERATIONS 审中-公开
标题翻译：非易失性存储器和节省读取和程序验证操作的方法
公开(公告)号：WO2006101500A1
公开(公告)日：2006-09-28
申请号：PCT/US2005/016516
申请日：2005-05-10
申请人： SANDISK CORPORATION , LI, Yan , LEE, Seungpil , CHAN, Siu Lung
发明人： LI, Yan , LEE, Seungpil , CHAN, Siu Lung
IPC分类号： G11C11/56
CPC分类号： G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.
摘要翻译：能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。另一方面，通过预先启动延长周期的任何操作来最小化功耗周期。在程序/验证操作中，不编程的单元在程序阶段中将其位线充电。当一组这些位线避免在每个程序阶段的过程中重新充电时，节省电力。

2. 发明申请

WO2010042587A1 NONVOLATILE MEMORY AND METHOD WITH REDUCED PROGRAM VERIFY BY IGNORING FASTEST AND/OR SLOWEST PROGRAMMING BITS 审中-公开
标题翻译：非易失性存储器和方法通过点燃最慢和/或更慢的编程位置来减少程序验证
公开(公告)号：WO2010042587A1
公开(公告)日：2010-04-15
申请号：PCT/US2009/059799
申请日：2009-10-07
申请人： SANDISK CORPORATION , LI, Yan , FONG, Yupin, Kawing , CHAN, Siu Lung
发明人： LI, Yan , FONG, Yupin, Kawing , CHAN, Siu Lung
IPC分类号： G11C11/56
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.
摘要翻译：一组非易失性存储器单元通过一系列递增编程脉冲在编程过程中被编程，其中每个脉冲之后是程序验证和可能的编程禁止步骤。在编程过程中，通过延迟启动和过早终止划分多个存储器状态的各种验证电平来提高性能。这相当于跳过组中最快和最慢编程（边缘）单元的验证和禁止步骤。当最快的单元格相对于第一验证电平全部被程序验证时，建立参考脉冲。什么脉冲上的什么验证电平的开始将相对于参考脉冲被延迟。当相对于该给定级别只有预定数量的单元格未被验证时，验证给定验证级别的停止。由边缘单元的过度编程或编程不足引起的任何错误都由纠错码进行校正。

3. 发明申请

WO2007076414A2 REFERENCE SENSE AMPLIFIER AND METHOD FOR COMPENSATED SENSING IN NON-VOLATILE MEMORY 审中-公开
标题翻译：参考灵敏放大器和用于非易失性存储器中的补偿感测的方法
公开(公告)号：WO2007076414A2
公开(公告)日：2007-07-05
申请号：PCT/US2006/062429
申请日：2006-12-20
申请人： SANDISK CORPORATION , CHAN, Siu Lung , CERNEA, Raul-adrian
发明人： CHAN, Siu Lung , CERNEA, Raul-adrian
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/14 , G11C16/26 , G11C16/32 , G11C2207/063
摘要： One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.
摘要翻译：用于感测非易失性存储器的传导电流的一个或多个感测放大器由具有类似特性和操作条件的参考感测放大器定时的信号控制。在一个方面中，感测周期由感测参考电流的参考感测放大器何时检测到预期状态来确定。另一方面，放大输出的积分周期由参考读出放大器何时输出预期状态来确定。当这些确定的时序用于控制一个或多个读出放大器时，跟踪环境和系统变化。

4. 发明申请

WO2006105363A1 NON-VOLATILE MEMORY AND METHOD WITH CONTROL GATE COMPENSATION FOR SOURCE LINE BIAS ERRORS 审中-公开
标题翻译：非挥发性记忆和方法与控制门补偿源线偏差错误
公开(公告)号：WO2006105363A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/011824
申请日：2006-03-29
申请人： SANDISK CORPORATION , CERNEA, Raul-Adrian , CHAN, Siu Lung
发明人： CERNEA, Raul-Adrian , CHAN, Siu Lung
IPC分类号： G11C16/34 , G11C16/08
CPC分类号： G11C16/3427 , G11C16/08 , G11C16/3418 , G11C2216/14
摘要： Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.
摘要翻译：源极偏置是由读/写电路的接地回路中的非零电阻引起的误差。在感测期间，存储器单元的源极被电阻两端的电压降错误地偏置，并导致施加的控制栅极和漏极电压的误差。当施加的控制栅极和漏极电压的参考点尽可能靠近存储器单元的源极时，该误差被最小化。在一个优选实施例中，参考点位于施加源极控制信号的节点处。当存储器阵列被组织在并行感测的存储器单元的页面中时，每个页面中的源耦合到页面源行，参考点被选择为经由复用器处于所选页面的页面源行。

5. 发明申请

WO2007076512A2 METHODS AND DEVICE FOR IMPROVED PROGRAM-VERIFY OPERATIONS IN NON-VOLATILE MEMORIES 审中-公开
标题翻译：用于改进非易失性记忆中的程序验证操作的方法和装置
公开(公告)号：WO2007076512A2
公开(公告)日：2007-07-05
申请号：PCT/US2006/062627
申请日：2006-12-27
申请人： SANDISK CORPORATION , CHAN, Siu Lung
发明人： CHAN, Siu Lung
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C16/3454 , G11C16/3459
摘要： In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.
摘要翻译：在编程涉及交替施加编程脉冲和验证编程的非易失性存储器时，根据存储器单元的状态，时间被保存在编程验证部分中，其中验证的一部分操作被认为是多余的并被跳过。优选地，在相对于用于在两个存储器状态之间划界的分界阈值水平的编程验证操作中，验证操作包括两个验证子周期的序列，第一子周期执行相对于第一阈值水平的验证，裕量低于分界阈值水平，并且第二子周期相对于与分界阈值水平相同的第二阈值水平执行验证。与传统情况不同，直到该组中的任何一个存储器单元已经被验证通过第一阈值为止，才执行第二子周期。

6. 发明申请

WO2006107706A1 NON-VOLATILE MEMORY AND METHOD WITH COMPENSATION FOR SOURCE LINE BIAS ERRORS 审中-公开
标题翻译：非易失性存储器和补偿源线偏差的方法
公开(公告)号：WO2006107706A1
公开(公告)日：2006-10-12
申请号：PCT/US2006/011675
申请日：2006-03-29
申请人： SANDISK CORPORATION , CERNEA, Raul-Adrian , CHAN, Siu Lung
发明人： CERNEA, Raul-Adrian , CHAN, Siu Lung
IPC分类号： G11C16/30 , G11C5/14
CPC分类号： G11C16/30 , G11C7/02 , G11C7/06 , G11C7/1051 , G11C7/1078 , G11C7/12
摘要： Source line bias (virtual ground) is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.
摘要翻译：源极偏置（虚地）是由读/写电路的接地回路中的非零电阻引入的误差。在感测期间，存储器单元的源极被电阻两端的电压降错误地偏置，并导致施加的控制栅极和漏极电压的误差。当施加的控制栅极和漏极电压的参考点尽可能靠近存储器单元的源极时，该误差被最小化。在一个优选实施例中，参考点位于施加源极控制信号的节点处。当存储器阵列被组织在并行感测的存储器单元的页面中时，每个页面中的源耦合到页面源行，参考点被选择为经由复用器处于所选页面的页面源行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式