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1. 发明申请

WO2007062307A2 METHOD AND MEMORY SYSTEM FOR LEGACY HOSTS 审中-公开
标题翻译：方法和存储系统的盗版主机
公开(公告)号：WO2007062307A2
公开(公告)日：2007-05-31
申请号：PCT/US2006060932
申请日：2006-11-15
申请人： SANDISK CORP , GUTERMAN DANIEL C , CEDAR YORAM , SCHROTER CHARLES , BARROCAS MILTON LOURENCO , GONZALEZ CARLOS , CONLEY KEVIN M
发明人： GUTERMAN DANIEL C , CEDAR YORAM , SCHROTER CHARLES , BARROCAS MILTON LOURENCO , GONZALEZ CARLOS , CONLEY KEVIN M
CPC分类号： G06F13/385 , G06F3/0607 , G06F3/064 , G06F3/0679 , G06F11/1068 , G11C7/1006 , G11C2207/104
摘要： A non-volatile memory device is provided with a controller and includes method that controls memory operations and to emulate the memory and communication characteristics of a legacy memory device. In this way, the memory device is compatible with a host that was originally designed to operate the legacy memory device. In particular, the controller performs the emulation to the host taking into account differences such as multibit memory, error correction requirement, memory support of overwrites, and erasable block sizes.
摘要翻译：非挥发性存储器件具有控制器，并且包括控制存储器操作并模拟传统存储器件的存储器和通信特性的方法。以这种方式，存储器设备与最初设计用于操作传统存储设备的主机兼容。特别地，控制器考虑到诸如多位存储器，错误校正要求，覆盖的存储器支持以及可擦除块大小之类的差异，对主机执行仿真。

2. 发明申请

WO0217330A3 NOVEL METHOD AND STRUCTURE FOR RELIABLE DATA COPY OPERATION FOR NON-VOLATILE MEMORIES 审中-公开
标题翻译：用于非易失性存储器的可靠数据复制操作的新方法和结构
公开(公告)号：WO0217330A3
公开(公告)日：2002-06-27
申请号：PCT/US0125678
申请日：2001-08-16
申请人： SANDISK CORP , CONLEY KEVIN M , GUTERMAN DANIEL C , GONZALEZ CARLOS J
发明人： CONLEY KEVIN M , GUTERMAN DANIEL C , GONZALEZ CARLOS J
IPC分类号： G06F12/16 , G06F12/00 , G06F12/06 , G11C16/02 , G11C16/06 , G11C16/10
CPC分类号： G11C16/102 , G11C16/105
摘要： An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with a duplicity of data registers and a controller circuit. When data are read from a flash array into a data register, the data is copied to a second register so that, during the ensuing program operation into the same array, the data may be transferred to the controller for the purpose of checking the data validity. This creates an improved performance system that doesn't suffer data transfer latency during copy operations but that is able to guarantee the validity of the data involved in such operations.
摘要翻译：改进的基于闪存的EEPROM存储子系统包括一个或多个闪存阵列，每个闪存阵列都有一个数据寄存器和一个控制器电路。当数据从闪存阵列读入数据寄存器时，数据被复制到第二个寄存器，以便在随后的程序操作进入同一个阵列的过程中，可以将数据传送到控制器以检查数据有效性。这创建了一个改进的性能系统，它在复制操作期间不会遭受数据传输延迟，但能够保证涉及这些操作的数据的有效性。

3. 发明申请

WO2005036401A3 FLASH MEMORY DATA CORRECTION AND SCRUB TECHNIQUES 审中-公开
标题翻译：闪存存储器数据校正和SCRUB技术
公开(公告)号：WO2005036401A3
公开(公告)日：2005-07-28
申请号：PCT/US2004031788
申请日：2004-09-28
申请人： SANDISK CORP , GONZALEZ CARLOS J , CONLEY KEVIN M
发明人： GONZALEZ CARLOS J , CONLEY KEVIN M
IPC分类号： G06F11/10
CPC分类号： G06F11/106 , G06F11/1068 , G11C8/08
摘要： In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase.
摘要翻译：为了保持存储在闪速存储器中的数据的完整性，其易于被存储器的相邻区域中的操作干扰，干扰事件导致在变得如此损坏之前读取，校正和重新写入数据，使得有效数据不能被收回。当存储器系统具有执行其他高优先级操作时，通过推迟执行某些纠正措施来平衡维护数据完整性和系统性能的有时冲突的需求。在使用非常大的擦除单位的存储器系统中，以与有效地重写远远小于擦除单位的容量的数据量相一致的方式执行校正处理。

4. 发明申请

WO2005066794A3 ADAPTIVE MODE SWITCHING OF FLASH MEMORY ADDRESS MAPPING BASED ON HOST USAGE CHARACTERISTICS 审中-公开
标题翻译：基于主机使用特性的FLASH存储器地址映射的自适应模式切换
公开(公告)号：WO2005066794A3
公开(公告)日：2005-11-10
申请号：PCT/US2004042862
申请日：2004-12-16
申请人： SANDISK CORP , GONZALEZ CARLOS J , SOMPEL MARK , CONLEY KEVIN M
发明人： GONZALEZ CARLOS J , SOMPEL MARK , CONLEY KEVIN M
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F12/0607 , G06F12/0246 , G06F2212/7202 , G06F2212/7208
摘要： In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism.
摘要翻译：在诸如闪存EEPROM系统的非易失性存储器存储系统中，响应于主机编程和控制器数据整合模式，控制器将数据扇区映射到块和元块的方式切换，以便提高性能和减少磨损。数据以不同程度的并行编程进入内存。

5. 发明申请

WO2005088456A3 FLASH CONTROLLER CACHE ARCHITECTURE 审中-公开
标题翻译：闪存控制器缓存架构
公开(公告)号：WO2005088456A3
公开(公告)日：2006-04-20
申请号：PCT/US2005007313
申请日：2005-03-07
申请人： SANDISK CORP , CONLEY KEVIN M , ELHAMIAS REUVEN
发明人： CONLEY KEVIN M , ELHAMIAS REUVEN
IPC分类号： G11C16/06 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0804 , G06F12/0866 , G06F2212/2022 , G06F2212/214 , G06F2212/2146 , G06F2212/282 , G06F2212/502
摘要： A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.
摘要翻译：介于非易失性存储器和主机之间的缓冲器高速缓存可被划分成可以不同策略操作的段。缓存策略包括直写，写入和预读。直写和回写策略可能会提高速度。预读高速缓存允许在缓冲器高速缓存和非易失性存储器之间更有效地使用总线。会话命令允许通过保证防止功率损耗来将数据保存在易失性存储器中。

6. 发明申请

WO2007133963A2 NONVOLATILE MEMORY WITH CONVOLUTIONAL CODING 审中-公开
标题翻译：非易失性存储器，具有调制编码
公开(公告)号：WO2007133963A2
公开(公告)日：2007-11-22
申请号：PCT/US2007068224
申请日：2007-05-04
申请人： SANDISK CORP , CONLEY KEVIN M
发明人： CONLEY KEVIN M
IPC分类号： G11C11/56 , G11C7/10 , G11C16/10 , G11C29/42
CPC分类号： G11C29/52 , G06F11/1068 , G11C7/02 , G11C7/1006 , G11C2029/0409
摘要： Data are encoded using convolutional coding prior to storage in a nonvolatile memory array, so that errors that occur when the data are read may be corrected even where there is a large number of such errors. Coding rates of less than one increase the amount of data to be stored but allow correction of large numbers of errors.
摘要翻译：在存储在非易失性存储器阵列中之前，使用卷积编码对数据进行编码，从而即使存在大量的这种错误也可以校正当读取数据时发生的错误。小于1的编码速率增加要存储的数据量，但允许校正大量错误。

7. 发明申请

WO2008042598A3 INVOLATILE MEMORY WITH SOFT-INPUT,SOFT-OUTPUT (SISO) DECODER, STATISTICAL UNIT AND ADAPTIVE OPERATION 审中-公开
标题翻译：具有软输入，软输出（SISO）解码器，统计单元和自适应操作的相关存储器
公开(公告)号：WO2008042598A3
公开(公告)日：2008-06-19
申请号：PCT/US2007078841
申请日：2007-09-19
申请人： SANDISK CORP , BRANDMAN YIGAL , CONLEY KEVIN M
发明人： BRANDMAN YIGAL , CONLEY KEVIN M
IPC分类号： G11C16/34 , G06F11/10 , G11C29/52
CPC分类号： G11C16/3418 , G06F11/1068 , G11C16/04 , G11C29/021 , G11C29/028 , G11C29/50004 , G11C29/52 , G11C2029/0409
摘要： In a nonvolatile memory system a Soft-Input Soft-Output (SISO) decoder corrects errors in data that is read from a memory and a statistical unit connected to the SISO decoder collects data regarding corrections. The statistical unit generates at least one output based on the collected data and at least one operating parameter of the memory is modified in response to the output.
摘要翻译：在非易失性存储器系统中，软输入软输出（SISO）解码器校正从存储器读取的数据中的错误，并且连接到SISO解码器的统计单元收集关于校正的数据。统计单元基于收集的数据生成至少一个输出，并且响应于输出修改存储器的至少一个操作参数。

8. 发明申请

WO2007079357A3 VOICE CONTROLLED PORTABLE MEMORY STORAGE DEVICE 审中-公开
标题翻译：语音控制的便携式存储设备
公开(公告)号：WO2007079357A3
公开(公告)日：2007-12-13
申请号：PCT/US2006062336
申请日：2006-12-19
申请人： SANDISK CORP , CONLEY KEVIN M
发明人： CONLEY KEVIN M
IPC分类号： G10L15/26
CPC分类号： G10L15/22 , G10L15/26
摘要： A portable memory device ("device") is provided. The device includes a microphone for receiving a voice command from a user; and a device controller that creates a voice based template for the voice command and stores the voice based template in a plurality of non-volatile memory cells, wherein the voice based template is associated with one or more button control actions entered by the user for certain device functionality. A method for a portable memory device is provided. The method includes, recording a keyword and creating a voice based template for the keyword, wherein a processor for the portable memory device creates the voice based template and stores the voice based template in non-volatile memory cells; prompting the user to capture button control actions related to a portable memory device functionality; and associating the button control actions to the voice based template.
摘要翻译：便携式存储器设备（“设备”）被提供。该设备包括用于接收来自用户的语音命令的麦克风; 以及设备控制器，其为语音命令创建基于语音的模板并将基于语音的模板存储在多个非易失性存储器单元中，其中基于语音的模板与由用户输入的一个或多个按钮控制动作相关联设备功能。提供了一种用于便携式存储器设备的方法。该方法包括记录关键字并为关键字创建基于语音的模板，其中用于便携式存储器设备的处理器创建基于语音的模板并将基于语音的模板存储在非易失性存储器单元中; 提示用户捕捉与便携式存储设备功能有关的按钮控制动作; 并将按钮控制动作与基于语音的模板相关联。

9. 发明申请

WO2007056669A3 ENHANCED FIRST LEVEL STORAGE CACHE USING NONVOLATILE MEMORY 审中-公开
标题翻译：使用非易失性存储器增强第一级存储缓存
公开(公告)号：WO2007056669A3
公开(公告)日：2007-09-20
申请号：PCT/US2006060490
申请日：2006-11-02
申请人： SANDISK CORP , CONLEY KEVIN M , THOMPSON E EARLE
发明人： CONLEY KEVIN M , THOMPSON E EARLE
IPC分类号： G06F12/08
CPC分类号： G06F12/0866 , G06F2212/2112 , G06F2212/222 , Y02D10/13
摘要： A detachable memory module is interposed between a host and a disk drive. The memory module includes a solid-state nonvolatile memory used for caching data sent by the host for storage in the disk drive. Caching takes place under the control of a memory controller in the memory module and may be transparent to the host. The disk drive may remain spun-down when data is cached, saving power. The destination for host data may be determined based on desired speed, power consumption and expected need for that data. A host may send specific commands to the memory module to enable additional functions.
摘要翻译：可拆卸的存储器模块插在主机和磁盘驱动器之间。存储器模块包括用于缓存由主机发送以存储在磁盘驱动器中的数据的固态非易失性存储器。缓存在存储器模块中的存储器控制器的控制下进行，并且可能对主机是透明的。数据缓存时，磁盘驱动器可能保持静音，节省电力。可以基于期望的速度，功率消耗和对该数据的预期需要来确定主机数据的目的地。主机可以向存储器模块发送特定命令以启用附加功能。

10. 发明申请

WO2005114670B1 PIPELINED DATA RELOCATION AND IMPROVED CHIP ARCHITECTURES 审中-公开
标题翻译：管道数据转移和改进的芯片架构
公开(公告)号：WO2005114670B1
公开(公告)日：2006-02-09
申请号：PCT/US2005016341
申请日：2005-05-09
申请人： SANDISK CORP , GOROBETS SERGEY ANATOLIEVICH , CONLEY KEVIN M
发明人： GOROBETS SERGEY ANATOLIEVICH , CONLEY KEVIN M
IPC分类号： G06F3/00 , G11C7/10 , G11C16/34 , G11C29/00
CPC分类号： G06F12/0246 , G06F11/1008 , G11C7/1039 , G11C7/1051 , G11C16/3436
摘要： The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improve are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.
摘要翻译：本发明提出了用于具有写入操作的读取操作的流水线的方法和架构。特别地，提出了用于流水线数据迁移操作的方法，其允许在控制器被重写之前检查和校正控制器中的数据，但是减少或消除通常会产生的额外时间损失。描述了许多架构改进以便于这些方法，包括：在存储器上引入两个寄存器，每个寄存器可由控制器独立访问; 允许在写入第二个寄存器时写入第一个存储器寄存器; 在存储器中引入两个寄存器，其中寄存器的内容可以交换。

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