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1. 发明申请

WO2013005343A1 APPARATUS AND METHOD FOR A MARKER GUIDED DATA TRANSFER BETWEEN A SINGLE MEMORY AND AN ARRAY OF MEMORIES WITH UNEVENLY DISTRIBUTED DATA AMOUNT IN AN SIMD PROCESSOR SYSTEM 审中-公开
标题翻译：用于在SIMD处理器系统中具有未分配数据量的单个存储器和存储器阵列之间的标记引导数据传输的装置和方法
公开(公告)号：WO2013005343A1
公开(公告)日：2013-01-10
申请号：PCT/JP2011/065739
申请日：2011-07-01
申请人： Renesas Electronics Corporation , LIESKE, Hanno
发明人： LIESKE, Hanno
IPC分类号： G06F13/42 , G06F15/16
CPC分类号： G06F13/4234 , G06F15/8015
摘要： An end marker setting unit sets an end marker at an end of a data stream stored inside memory elements. When transferring data from a processing element array to a single memory over a bus system, in the case that the end marker is detected regarding certain processing element, a marker evaluation unit for write direction deletes the data which is transferred from that processing element in the following rows. And when transferring data from the single memory to the processing element array, in the case that the end marker for certain processing element is detected, a marker evaluation unit for read direction inserts data for that processing element in the following row.
摘要翻译：结束标记设置单元在存储在存储元件内的数据流的末尾设置结束标记。当通过总线系统将数据从处理元件阵列传送到单个存储器时，在检测到关于某个处理元件的结束标记的情况下，用于写入方向的标记评估单元删除从该处理元件传送的数据以下行。并且当将数据从单个存储器传送到处理元件阵列时，在检测到特定处理元件的结束标记的情况下，用于读取方向的标记评估单元插入下一行中该处理元件的数据。

2. 发明申请

WO2012120690A1 DATA TRANSFERRING METHOD, DMA CONTROLLER AND IMAGE PROCESSING DEVICE 审中-公开
标题翻译：数据传输方法，DMA控制器和图像处理设备
公开(公告)号：WO2012120690A1
公开(公告)日：2012-09-13
申请号：PCT/JP2011/055873
申请日：2011-03-08
申请人： Renesas Electronics Corporation , LIESKE, Hanno
发明人： LIESKE, Hanno
IPC分类号： G06F13/28 , G09G5/00
CPC分类号： G06F13/28 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2360/123 , G09G2360/127
摘要： Provided is a data transferring method for transferring interlaced Region of interest (ROI)data stored in a first memory (EMEM) to a second memory (IMEM) as non-interlaced data using direct memory access control (240). This method comprises setting values of EMEM_start_address, element_width, ROI_width, element_offset, ROI_height, and ROI_offset. Further, this method includes reading out data from the first memory to an input buffer, calculating positions of data to be extracted, extracting data corresponding to calculated position from the input buffer (221) and storing them in an output buffer (222), and sending data stored in the output buffer to the second memory.
摘要翻译：提供了一种用于使用直接存储器访问控制（240）将存储在第一存储器（EMEM）中的隔行扫描区域（ROI）数据传送到第二存储器（IMEM））作为非隔行扫描数据的数据传送方法。该方法包括设置EMEM_start_address，element_width，ROI_width，element_offset，ROI_height和ROI_offset的值。此外，该方法包括从第一存储器向输入缓冲器读出数据，计算要提取的数据的位置，从输入缓冲器（221）提取与计算出的位置相对应的数据并将其存储在输出缓冲器（222）中，以及将存储在输出缓冲器中的数据发送到第二存储器。

3. 发明申请

WO2013046475A1 APPARATUS AND METHOD OF A CONCURRENT DATA TRANSFER OF MULTIPLE REGIONS OF INTEREST (ROI) IN AN SIMD PROCESSOR SYSTEM 审中-公开
标题翻译： SIMD处理器系统中多个利益区域（ROI）的并行数据传输的装置和方法
公开(公告)号：WO2013046475A1
公开(公告)日：2013-04-04
申请号：PCT/JP2011/072715
申请日：2011-09-27
申请人： Renesas Electronics Corporation , LIESKE, Hanno
发明人： LIESKE, Hanno
IPC分类号： G06F15/80 , G06F9/345 , G06T1/20
CPC分类号： G06F15/8015 , G06F9/345 , G06F9/383 , G06F9/3887 , G06F15/167 , G06F2211/002 , G06T1/60
摘要： This present invention provides a fast data transfer for a concurrent transfer of multiple ROI areas between an internal memory array and a single memory where each PE can specify the parameter set for the area to be transferred independently from the other PE. For example, for a read transfer, the requests are generated in a way that first the first element of each ROI area is requested from the single memory for each PE before the following elements of each ROI area are requested. After the first element from each ROI area has been received from the single memory in a control processor and has been transferred from the control processor over a bus system to the internal memory array, all elements are in parallel stored to the internal memory array. Then, the second element of each ROI area is requested from the single memory for each PE. The transfer finishes after all elements of each ROI area are transferred to their assigned PEs.
摘要翻译：本发明提供了用于在内部存储器阵列和单个存储器之间并行传送多个ROI区域的快速数据传输，其中每个PE可以独立于另一个PE指定要传送的区域的参数集。例如，对于读取传送，请求以这样一种方式生成：在请求每个ROI区域的以下元素之前，首先从每个PE的单个存储器请求每个ROI区域的第一个元素。在来自每个ROI区域的第一个元件已经从控制处理器中的单个存储器接收到并且已经通过总线系统从控制处理器传送到内部存储器阵列之后，所有元件被并行地存储到内部存储器阵列中。然后，从每个PE的单个存储器请求每个ROI区域的第二个元素。转移完成后，每个ROI区域的所有元素都被转移到其分配的PE。

4. 发明申请

WO2012032666A2 INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD 审中-公开
标题翻译：信息处理设备和信息处理方法
公开(公告)号：WO2012032666A2
公开(公告)日：2012-03-15
申请号：PCT/JP2010/065684
申请日：2010-09-06
申请人： NEC Corporation , LIESKE, Hanno
发明人： LIESKE, Hanno
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/02 , G06F12/0875 , G06F12/0886 , G06F2212/1016 , H04N19/11 , H04N19/17 , H04N19/423 , H04N19/61
摘要： An information processing device includes an internal memory which is capable of performing processing faster than an external memory, and a memory controller which controls data transfer between the internal memory and the external memory. The memory controller controls a first data transfer and a second data transfer. The first data transfer is a data transfer from the external memory to the internal memory, and the second data transfer is a data transfer from the internal memory to the external memory. The second data transfer transfers a part of the data area of the internal memory transferred in the first data transfer, and the data area which is read out in a non-continuous way from the internal memory is transferred in place to the external memory in the second data transfer.
摘要翻译：信息处理装置包括能够比外部存储器执行处理的内部存储器，以及控制内部存储器和外部存储器之间的数据传送的存储器控制器。存储器控制器控制第一数据传送和第二数据传送。第一数据传输是从外部存储器到内部存储器的数据传送，第二数据传输是从内部存储器到外部存储器的数据传送。第二数据传送传送在第一数据传送中传输的内部存储器的一部分数据区域，并且以非连续方式从内部存储器读出的数据区域被传送到外部存储器第二次数据传输。

5. 发明申请

WO2008108005A1 A DATA TRANSFER NETWORK AND CONTROL APPARATUS FOR A SYSTEM WITH AN ARRAY OF PROCESSING ELEMENTS EACH EITHER SELF- OR COMMON CONTROLLED 审中-公开
标题翻译：一种用于具有每个处理单元的系统的系统的数据传输网络和控制装置，每个系统均由自身或通用控制
公开(公告)号：WO2008108005A1
公开(公告)日：2008-09-12
申请号：PCT/JP2007/054756
申请日：2007-03-06
申请人： NEC CORPORATION , LIESKE, Hanno , KYO, Shorin
发明人： LIESKE, Hanno , KYO, Shorin
IPC分类号： G06F15/173 , G06F15/80 , G06F13/16
CPC分类号： G06F13/1605 , G06F15/8007
摘要： A processor of SIMD/MIMD dual mode architecture comprises common controlled first processing elements, self-controlled second processing elements and a pipelined (ring) network connecting the first PEs and the second PEs sequentially. An access controller has access control lines, each access control line being connected to each PE of the first and second PEs to control data access timing between each PE and the network. Each PE can be self-controlled or common controlled, such as dual mode SIMD/MIMD architectures, reducing the wiring area requirement.
摘要翻译： SIMD / MIMD双模架构的处理器包括共同控制的第一处理元件，自我控制的第二处理元件和连续地连接第一PE和第二PE的流水线（环形）网络。访问控制器具有访问控制线，每个访问控制线连接到第一和第二PE的每个PE，以控制每个PE和网络之间的数据访问定时。每个PE可以是自我控制或共同控制的，例如双模式SIMD / MIMD体系结构，减少接线面积要求。

6. 发明申请

WO2010113340A1 SINGLE INSTRUCTION MULTIPLE DATA (SIMD) PROCESSOR HAVING A PLURALITY OF PROCESSING ELEMENTS INTERCONNECTED BY A RING BUS 审中-公开
标题翻译：具有多个加工元件的单指令多数据（SIMD）处理器由一个环形总线连接
公开(公告)号：WO2010113340A1
公开(公告)日：2010-10-07
申请号：PCT/JP2009/067282
申请日：2009-09-25
申请人： NEC CORPORATION , LIESKE, Hanno
发明人： LIESKE, Hanno
IPC分类号： G06F15/163 , G06F15/173 , G06F15/80 , H04N5/44 , H04N7/26
CPC分类号： G06F15/8015 , G06F15/163 , G06F15/17337 , H04N5/44 , H04N19/00 , H04N19/436 , H04N19/44 , H04N19/61
摘要： A single instruction multiple data (SIMD) processor having a plurality of processing elements and including: a splitting unit for splitting an address of the read-only parameter data in the data memory into a first part and a second part at a bit position corresponding to the number of the processor elements; and a comparing unit for comparing the number of shifting, on a ring bus, of the read-only parameter data, which is taken from the internal memory at the address in accordance with the first part, with a difference between an own processor element position and a portion of the global address of the read-only parameter data to be accessed, the portion designating a position in the ring of the processor element in which the read-only parameter data to be accessed is stored and corresponding to the second part, to cause the other processor elements to take the read-only parameter data.
摘要翻译：一种具有多个处理元件的单指令多数据（SIMD）处理器，包括：分割单元，用于将数据存储器中的只读参数数据的地址分割成与第一部分和第二部分相对应的比特位置处理器元件的数量; 以及比较单元，用于比较在环形总线上从根据第一部分的地址处的内部存储器获取的只读参数数据与自身处理器单元位置之间的差异以及要访问的只读参数数据的全局地址的一部分，指定处理器元件的环中的位置的部分，其中存储要访问的只读参数数据并对应于第二部分，以使其他处理器元件采用只读参数数据。

7. 发明申请

WO2009110100A1 A CONTROL APPARATUS FOR FAST INTER PROCESSING UNIT DATA EXCHANGE IN A PROCESSOR ARCHITECTURE WITH PROCESSING UNITS OF DIFFERENT BANDWIDTH CONNECTION TO A PIPELINED RING BUS 审中-公开
标题翻译：用于处理器架构中的快速处理单元数据交换的控制装置，具有与管道连接总线的不同带宽连接的处理单元
公开(公告)号：WO2009110100A1
公开(公告)日：2009-09-11
申请号：PCT/JP2008/054224
申请日：2008-03-03
申请人： NEC CORPORATION , LIESKE, Hanno , KYO, Shorin
发明人： LIESKE, Hanno , KYO, Shorin
IPC分类号： G06F13/40 , G06F15/80 , G06F13/364
CPC分类号： G06F13/4018 , G06F15/8007
摘要： Nowadays, many processor architectures have processing units with different bandwidth requirements which are connected over a pipelined ring bus. The proposed invention can optimize the data transfer for the case where processing units with lower bandwidth requirements can be grouped and controlled together for a data transfer, so that the available bus bandwidth can be optimally utilized.
摘要翻译：如今，许多处理器架构具有通过流水线环形总线连接的具有不同带宽要求的处理单元。所提出的发明可以优化数据传输，其中具有较低带宽要求的处理单元可以被分组并一起控制用于数据传送，从而可以最佳地利用可用的总线带宽。

8. 发明申请

WO2011064898A1 APPARATUS TO ENABLE TIME AND AREA EFFICIENT ACCESS TO SQUARE MATRICES AND ITS TRANSPOSES DISTRIBUTED STORED IN INTERNAL MEMORY OF PROCESSING ELEMENTS WORKING IN SIMD MODE AND METHOD THEREFORE 审中-公开
标题翻译：使用时间和区域有效访问方形矩阵及其分配的存储在处理元件的内部存储器中的传输的方法和方法
公开(公告)号：WO2011064898A1
公开(公告)日：2011-06-03
申请号：PCT/JP2009/070272
申请日：2009-11-26
申请人： NEC CORPORATION , LIESKE, Hanno
发明人： LIESKE, Hanno
IPC分类号： G06F15/173 , G06F15/80
CPC分类号： G06F15/8015
摘要： Disclosed is an apparatus having a plurality of processing elements which work in single instruction, multiple data (SIMD) mode. The processing elements have internal memory units. Instead of a full crossbar connection, only connections from each processing element to selected internal memory units are provided. These internal memory connections are selected in a way to enable time and area efficient access only to the own internal memory for direct access to matrix stored in a distributed manner in the internal memory units and to internal memory units which are needed for the generation of the transposed matrix to perform a corner turn execution.
摘要翻译：公开了一种具有多个处理单元的装置，它们以单指令，多数据（SIMD）模式工作。处理元件具有内部存储单元。而不是完整的交叉开关连接，仅提供从每个处理元件到所选择的内部存储器单元的连接。选择这些内部存储器连接以使时间和区域仅有效地访问内部存储器，以便以分布式方式存储在内部存储器单元中的矩阵和用于生成内部存储器单元所需的内部存储器单元的直接访问转置矩阵执行转角执行。

9. 发明申请

WO2011052097A1 METHOD AND APPARATUS FOR PARALLEL H.264 IN-LOOP DE-BLOCKING FILTER IMPLEMENTATION 审中-公开
标题翻译：用于并行H.264嵌入式阻塞滤波器实现的方法和装置
公开(公告)号：WO2011052097A1
公开(公告)日：2011-05-05
申请号：PCT/JP2009/068948
申请日：2009-10-29
申请人： NEC Corporation , LIESKE, Hanno
发明人： LIESKE, Hanno
IPC分类号： H04N7/26 , H04N7/50
CPC分类号： H04N19/86 , H04N19/436 , H04N19/61 , H04N19/82
摘要： Compared to the related art, where the time distance in horizontal direction is 2 Synchronization Intervals (SI) between 2 Processing Units which are processing neighboring MB rows, the current invention enables to reduce the distance from 2 SIs to 1 SI, which increases the start-up phase performance. This is reached by dividing the filter task into sub tasks and reordering the execution order of these sub tasks. The sub tasks include a vertical edge filter task and a horizontal edge filter task. Further, the synchronization is scheduled in between the vertical edge filter task and the horizontal edge filter task.
摘要翻译：与现有技术相比，其中水平方向上的时间距离为2处理相邻MB行的2个处理单元之间的同步间隔（SI），本发明能够减少从2SI到1SI的距离，这增加了开始 - 相位性能。这是通过将过滤器任务划分为子任务并重新排序这些子任务的执行顺序来实现的。子任务包括垂直边缘过滤器任务和水平边缘过滤器任务。此外，在垂直边缘滤波器任务和水平边缘滤波器任务之间调度同步。

10. 发明申请

WO2016157246A1 DATA TRANSFER APPARATUS AND MICROCOMPUTER 审中-公开
标题翻译：数据传输设备和微型计算机
公开(公告)号：WO2016157246A1
公开(公告)日：2016-10-06
申请号：PCT/JP2015/001808
申请日：2015-03-30
申请人： RENESAS ELECTRONICS CORPORATION
发明人： LIESKE, Hanno
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： A two-row buffer (3) stores first and second rows. An input buffer (2) stores a third row. A gradient calculator (4) calculates first and second gradient values. A vote calculator (5) calculates a vote amount value. A direction calculator (6) calculates a vote direction value. An output buffer (8) stores accumulated vote amount values. An adder (7) adds the vote amount value to the received accumulated vote amount value and replaces the accumulated vote amount value in the output buffer (8) with the added value. The first gradient value is a difference between values of two pixels in the first and third row. The second gradient value is a difference between values of two pixels in the second row. The four pixels are immediately adjacent to a target pixel in the second row. The output buffer (8) outputs all of the accumulated vote amount values to an outside processor.
摘要翻译：两行缓冲器（3）存储第一行和第二行。输入缓冲器（2）存储第三行。梯度计算器（4）计算第一和第二梯度值。投票计算器（5）计算投票金额值。方向计算器（6）计算投票方向值。输出缓冲器（8）存储累积投票数值。加法器（7）将投票金额值添加到接收到的累计投票金额值，并用附加值代替输出缓冲器（8）中的积累投票金额值。第一个梯度值是第一行和第三行中两个像素的值之间的差值。第二梯度值是第二行中两个像素的值之间的差值。四个像素紧邻第二行中的目标像素。输出缓冲器（8）将所有积累的投票数值输出到外部处理器。

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