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1. 发明申请

WO2016157246A1 DATA TRANSFER APPARATUS AND MICROCOMPUTER 审中-公开
标题翻译：数据传输设备和微型计算机
公开(公告)号：WO2016157246A1
公开(公告)日：2016-10-06
申请号：PCT/JP2015/001808
申请日：2015-03-30
申请人： RENESAS ELECTRONICS CORPORATION
发明人： LIESKE, Hanno
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： A two-row buffer (3) stores first and second rows. An input buffer (2) stores a third row. A gradient calculator (4) calculates first and second gradient values. A vote calculator (5) calculates a vote amount value. A direction calculator (6) calculates a vote direction value. An output buffer (8) stores accumulated vote amount values. An adder (7) adds the vote amount value to the received accumulated vote amount value and replaces the accumulated vote amount value in the output buffer (8) with the added value. The first gradient value is a difference between values of two pixels in the first and third row. The second gradient value is a difference between values of two pixels in the second row. The four pixels are immediately adjacent to a target pixel in the second row. The output buffer (8) outputs all of the accumulated vote amount values to an outside processor.
摘要翻译：两行缓冲器（3）存储第一行和第二行。输入缓冲器（2）存储第三行。梯度计算器（4）计算第一和第二梯度值。投票计算器（5）计算投票金额值。方向计算器（6）计算投票方向值。输出缓冲器（8）存储累积投票数值。加法器（7）将投票金额值添加到接收到的累计投票金额值，并用附加值代替输出缓冲器（8）中的积累投票金额值。第一个梯度值是第一行和第三行中两个像素的值之间的差值。第二梯度值是第二行中两个像素的值之间的差值。四个像素紧邻第二行中的目标像素。输出缓冲器（8）将所有积累的投票数值输出到外部处理器。

2. 发明申请

WO2016125202A1 DATA TRANSFER APPARATUS 审中-公开
标题翻译：数据传输设备
公开(公告)号：WO2016125202A1
公开(公告)日：2016-08-11
申请号：PCT/JP2015/000482
申请日：2015-02-04
申请人： RENESAS ELECTRONICS CORPORATION
发明人： LIESKE, Hanno
IPC分类号： G06F13/16
CPC分类号： G06F13/1668
摘要： A data transfer apparatus (100) includes a processing unit (101), a memory bank array (4), and a memory controller (3). The processing unit (101) outputs a plurality of offset values and a base address. The memory bank array includes a plurality of memory banks (4). The memory controller (3) offsets the base address by the offset values to generate offset addresses, and reads data from the memory bank array (4) using the offset addresses. The memory controller receives the offset values and base address from the processing unit (101).
摘要翻译：数据传送装置（100）包括处理单元（101），存储体阵列（4）和存储器控制器（3）。处理单元（101）输出多个偏移值和基地址。存储体阵列包括多个存储体（4）。存储器控制器（3）通过偏移值偏移基址以产生偏移地址，并且使用偏移地址从存储体阵列（4）读取数据。存储器控制器从处理单元（101）接收偏移值和基地址。

3. 发明申请

WO2013046475A1 APPARATUS AND METHOD OF A CONCURRENT DATA TRANSFER OF MULTIPLE REGIONS OF INTEREST (ROI) IN AN SIMD PROCESSOR SYSTEM 审中-公开
标题翻译： SIMD处理器系统中多个利益区域（ROI）的并行数据传输的装置和方法
公开(公告)号：WO2013046475A1
公开(公告)日：2013-04-04
申请号：PCT/JP2011/072715
申请日：2011-09-27
申请人： Renesas Electronics Corporation , LIESKE, Hanno
发明人： LIESKE, Hanno
IPC分类号： G06F15/80 , G06F9/345 , G06T1/20
CPC分类号： G06F15/8015 , G06F9/345 , G06F9/383 , G06F9/3887 , G06F15/167 , G06F2211/002 , G06T1/60
摘要： This present invention provides a fast data transfer for a concurrent transfer of multiple ROI areas between an internal memory array and a single memory where each PE can specify the parameter set for the area to be transferred independently from the other PE. For example, for a read transfer, the requests are generated in a way that first the first element of each ROI area is requested from the single memory for each PE before the following elements of each ROI area are requested. After the first element from each ROI area has been received from the single memory in a control processor and has been transferred from the control processor over a bus system to the internal memory array, all elements are in parallel stored to the internal memory array. Then, the second element of each ROI area is requested from the single memory for each PE. The transfer finishes after all elements of each ROI area are transferred to their assigned PEs.
摘要翻译：本发明提供了用于在内部存储器阵列和单个存储器之间并行传送多个ROI区域的快速数据传输，其中每个PE可以独立于另一个PE指定要传送的区域的参数集。例如，对于读取传送，请求以这样一种方式生成：在请求每个ROI区域的以下元素之前，首先从每个PE的单个存储器请求每个ROI区域的第一个元素。在来自每个ROI区域的第一个元件已经从控制处理器中的单个存储器接收到并且已经通过总线系统从控制处理器传送到内部存储器阵列之后，所有元件被并行地存储到内部存储器阵列中。然后，从每个PE的单个存储器请求每个ROI区域的第二个元素。转移完成后，每个ROI区域的所有元素都被转移到其分配的PE。

4. 发明申请

WO2016051436A1 DATA TRANSFER APPARATUS 审中-公开
标题翻译：数据传输设备
公开(公告)号：WO2016051436A1
公开(公告)日：2016-04-07
申请号：PCT/JP2014/005020
申请日：2014-10-01
申请人： RENESAS ELECTRONICS CORPORATION
发明人： LIESKE, Hanno
IPC分类号： G06F12/08
CPC分类号： G06F12/0879 , G06F12/0862 , G06F12/0897 , G06F2212/1024
摘要： A data transfer apparatus (100) including a hierarchy memory system includes: a processing unit (1); a lower hierarchy level memory unit (3); an upper hierarchy level memory unit (2); a data transfer control unit (4); a bus (5); and a temporary memory unit (6). The data transfer control unit (4) reads data elements from the lower hierarchy level memory unit (3) in a single data transfer mode, and stores the read data elements to consecutive addresses in the temporary memory unit (6) as consecutive data. The data transfer control unit (4) reads the consecutive data from the temporary memory unit (6), and sends out the consecutive data to the upper hierarchy level memory unit (2) in a burst data transfer mode.
摘要翻译：一种包括层级存储器系统的数据传送装置（100），包括：处理单元（1）; 下层级存储单元（3）; 上层级存储单元（2）; 数据传送控制单元（4）; 一辆公共汽车（5）; 和临时存储单元（6）。数据传输控制单元（4）以单个数据传送模式从下层级存储单元（3）读取数据元素，并将读取的数据元素作为连续数据存储在临时存储器单元（6）中的连续地址。数据传送控制单元（4）从临时存储单元（6）读取连续数据，并以突发数据传送模式将连续数据发送到上层级存储单元（2）。

5. 发明申请

WO2016051435A1 DATA TRANSFER APPARATUS AND MICROCOMPUTER 审中-公开
标题翻译：数据传输设备和微型计算机
公开(公告)号：WO2016051435A1
公开(公告)日：2016-04-07
申请号：PCT/JP2014/005019
申请日：2014-10-01
申请人： RENESAS ELECTRONICS CORPORATION
发明人： LIESKE, Hanno
IPC分类号： G06F15/80
CPC分类号： G06F15/17375
摘要： A pipeline ring-bus system includes a ring bus and ring bus registers. Processing elements are connected to the ring bus between a former and latter ring bus registers. Each processing element sends out a request or response. The request or response stored in the former ring bus register is transferred to the latter ring bus register in each clock cycle. Each processing element includes a two-entry buffer. Each processing element receives different requests. Each processing element prepares different responses corresponding to the different requests. The different requests temporally overlap in a pipelined way.
摘要翻译：管道环形总线系统包括环形总线和环形总线寄存器。处理元件连接到前一个和后一个环形总线寄存器之间的环形总线。每个处理单元发出请求或响应。存储在前一个环形总线寄存器中的请求或响应在每个时钟周期内被传送到后一个环形总线寄存器。每个处理元件包括双入口缓冲器。每个处理元件接收不同的请求。每个处理单元根据不同的请求准备不同的响应。不同的请求以流水线方式暂时重叠。

6. 发明申请

WO2013005343A1 APPARATUS AND METHOD FOR A MARKER GUIDED DATA TRANSFER BETWEEN A SINGLE MEMORY AND AN ARRAY OF MEMORIES WITH UNEVENLY DISTRIBUTED DATA AMOUNT IN AN SIMD PROCESSOR SYSTEM 审中-公开
标题翻译：用于在SIMD处理器系统中具有未分配数据量的单个存储器和存储器阵列之间的标记引导数据传输的装置和方法
公开(公告)号：WO2013005343A1
公开(公告)日：2013-01-10
申请号：PCT/JP2011/065739
申请日：2011-07-01
申请人： Renesas Electronics Corporation , LIESKE, Hanno
发明人： LIESKE, Hanno
IPC分类号： G06F13/42 , G06F15/16
CPC分类号： G06F13/4234 , G06F15/8015
摘要： An end marker setting unit sets an end marker at an end of a data stream stored inside memory elements. When transferring data from a processing element array to a single memory over a bus system, in the case that the end marker is detected regarding certain processing element, a marker evaluation unit for write direction deletes the data which is transferred from that processing element in the following rows. And when transferring data from the single memory to the processing element array, in the case that the end marker for certain processing element is detected, a marker evaluation unit for read direction inserts data for that processing element in the following row.
摘要翻译：结束标记设置单元在存储在存储元件内的数据流的末尾设置结束标记。当通过总线系统将数据从处理元件阵列传送到单个存储器时，在检测到关于某个处理元件的结束标记的情况下，用于写入方向的标记评估单元删除从该处理元件传送的数据以下行。并且当将数据从单个存储器传送到处理元件阵列时，在检测到特定处理元件的结束标记的情况下，用于读取方向的标记评估单元插入下一行中该处理元件的数据。

7. 发明申请

WO2012120690A1 DATA TRANSFERRING METHOD, DMA CONTROLLER AND IMAGE PROCESSING DEVICE 审中-公开
标题翻译：数据传输方法，DMA控制器和图像处理设备
公开(公告)号：WO2012120690A1
公开(公告)日：2012-09-13
申请号：PCT/JP2011/055873
申请日：2011-03-08
申请人： Renesas Electronics Corporation , LIESKE, Hanno
发明人： LIESKE, Hanno
IPC分类号： G06F13/28 , G09G5/00
CPC分类号： G06F13/28 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2360/123 , G09G2360/127
摘要： Provided is a data transferring method for transferring interlaced Region of interest (ROI)data stored in a first memory (EMEM) to a second memory (IMEM) as non-interlaced data using direct memory access control (240). This method comprises setting values of EMEM_start_address, element_width, ROI_width, element_offset, ROI_height, and ROI_offset. Further, this method includes reading out data from the first memory to an input buffer, calculating positions of data to be extracted, extracting data corresponding to calculated position from the input buffer (221) and storing them in an output buffer (222), and sending data stored in the output buffer to the second memory.
摘要翻译：提供了一种用于使用直接存储器访问控制（240）将存储在第一存储器（EMEM）中的隔行扫描区域（ROI）数据传送到第二存储器（IMEM））作为非隔行扫描数据的数据传送方法。该方法包括设置EMEM_start_address，element_width，ROI_width，element_offset，ROI_height和ROI_offset的值。此外，该方法包括从第一存储器向输入缓冲器读出数据，计算要提取的数据的位置，从输入缓冲器（221）提取与计算出的位置相对应的数据并将其存储在输出缓冲器（222）中，以及将存储在输出缓冲器中的数据发送到第二存储器。

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