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1. 发明申请

WO2008136974A1 UNIVERSAL BRANCH IDENTIFIER FOR INVALIDATION OF SPECULATIVE INSTRUCTIONS 审中-公开
标题翻译：通用分支机构识别不定式说明书
公开(公告)号：WO2008136974A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/005509
申请日：2008-04-29
申请人： RMI CORPORATION , SINGH, Gaurav , SRINIVASAN, Srivatsan , RAMIREZ, Ricardo , CHEN, Wei-Hsiang , NGUYEN, Hai Ngoc
发明人： SINGH, Gaurav , SRINIVASAN, Srivatsan , RAMIREZ, Ricardo , CHEN, Wei-Hsiang , NGUYEN, Hai Ngoc
IPC分类号： G06F7/38
CPC分类号： G06F9/3842 , G06F9/3861
摘要： A system for speculative branch predictions. An embodiment of the system includes branch prediction logic, fetch logic, and branch identification logic. The branch prediction logic is configured to predict a branch path for a branch in an instruction stream. The fetch logic is coupled to the branch prediction logic. The fetch logic is configured to speculatively fetch an instruction corresponding to the predicted branch path. The branch identification logic is coupled to the branch prediction logic and the fetch logic. The branch identification logic is configured to mark the speculatively fetched instruction with a branch identifier using a universal branch identification format. The universal branch identification format includes a bit value at a bit position corresponding to the predicted branch path.
摘要翻译：投机分支预测系统。该系统的实施例包括分支预测逻辑，提取逻辑和分支识别逻辑。分支预测逻辑被配置为预测指令流中的分支的分支路径。提取逻辑耦合到分支预测逻辑。提取逻辑被配置为推测性地获取与预测的分支路径相对应的指令。分支识别逻辑耦合到分支预测逻辑和提取逻辑。分支识别逻辑被配置为使用通用分支标识格式使用分支标识符标记所推测的获取的指令。通用分支识别格式包括与预测分支路径相对应的比特位置处的比特值。

2. 发明申请

WO2009088396A3 AGE MATRIX FOR QUEUE DISPATCH ORDER 审中-公开
公开(公告)号：WO2009088396A3
公开(公告)日：2009-07-16
申请号：PCT/US2008/007723
申请日：2008-06-19
申请人： RMI CORPORATION , SRINIVASAN, Srivatsan , SINGH, Gaurav , WONG, Lintsung
发明人： SRINIVASAN, Srivatsan , SINGH, Gaurav , WONG, Lintsung
IPC分类号： G06F9/30
摘要： An apparatus for queue scheduling. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch indicators associated with a plurality of pairs of entries of the queue to indicate a write order of the entπes in the queue. The queue controller interfaces with the queue and the dispatch order data structure. Multiple queue structures interfaces with an output arbitration logic and schedule packets to achieve optimal throughput. An apparatus for queue allocation. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue.

3. 发明申请

WO2009130711A1 IMPROVED DIFFUSER FOR CANE OR BAGASSE 审中-公开
标题翻译：改进的扩散器适用于犬类或包囊
公开(公告)号：WO2009130711A1
公开(公告)日：2009-10-29
申请号：PCT/IN2009/000241
申请日：2009-04-21
申请人： SPRAY ENGINEERING DEVICES LIMITED , SINGH, Jai, Prakash , GUPTA, Vipin, Kumar , SINGH, Gaurav
发明人： SINGH, Jai, Prakash , GUPTA, Vipin, Kumar , SINGH, Gaurav
IPC分类号： C13D1/12 , B01D11/00
CPC分类号： B01D11/0223 , C13B10/12
摘要： The invention discloses an improved diffuser wherein the problems associated with diffusers with vertically disposed annular extraction stages when scaled to industrial level have been overcome by providing a simple but novel, economical and efficient solution. The improved diffuser has a smooth and continuous operation without requiring any additional or complex arrangements, controls or maintenance, as were required in the prior art.
摘要翻译：本发明公开了一种改进的扩散器，其中通过提供简单但新颖的，经济和有效的解决方案克服了当缩放到工业级时与垂直设置的环形提取级的扩散器相关的问题。改进的扩散器具有平滑和连续的操作，而不需要现有技术中所需的任何额外的或复杂的布置，控制或维护。

4. 发明申请

WO2010062916A1 NETWORK-ON-CHIP SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR TRANSMITTING MESSAGES UTILIZING A CENTRALIZED ON-CHIP SHARED MEMORY SWITCH 审中-公开
标题翻译：网络片上系统，方法和计算机程序产品，用于传输利用集中式片上共享存储器开关的消息
公开(公告)号：WO2010062916A1
公开(公告)日：2010-06-03
申请号：PCT/US2009/065802
申请日：2009-11-24
申请人： NETLOGIC MICROSYSTEMS, INC. , GARG, Gaurav , HASS, David T. , KUILA, Kaushik , SINGH, Gaurav
发明人： GARG, Gaurav , HASS, David T. , KUILA, Kaushik , SINGH, Gaurav
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L49/103 , H04L49/109
摘要： A network-on-chip system, method, and computer program product are provided for transmitting messages utilizing a centralized on-chip shared memory switch. In operation, a message is sent from one of a plurality of agents connected on a messaging network. The message is received at a central shared memory switch, the central shared memory switch being in communication with each of the plurality of agents. Further, the message is transmitted from the central shared memory switch to a destination agent, the destination agent being one of the plurality of agents.
摘要翻译：提供了片上系统，方法和计算机程序产品，用于使用集中的片上共享存储器交换机来发送消息。在操作中，从连接在消息收发网络上的多个代理之一发送消息。消息在中央共享存储交换机处被接收，中央共享存储器交换机与多个代理中的每一个进行通信。此外，消息从中央共享存储交换机发送到目的地代理，目的地代理是多个代理之一。

5. 发明申请

WO2004049645A1 ADVANCED TELECOMMUNICATIONS ROUTER AND CROSSBAR SWITCH CONTROLLER 审中-公开
标题翻译：高级电信路由器和交叉开关控制器
公开(公告)号：WO2004049645A1
公开(公告)日：2004-06-10
申请号：PCT/US2002/037571
申请日：2002-11-21
申请人： YANG, Brian, Hang Wai , SIU, Kai-Yeung, Sunny , LIEN, Wei-Han , SINGH, Gaurav
发明人： YANG, Brian, Hang Wai , SIU, Kai-Yeung, Sunny , LIEN, Wei-Han , SINGH, Gaurav
IPC分类号： H04L12/50
CPC分类号： H04L49/25 , H04L49/101 , H04L49/3027 , H04L49/3045
摘要： The invention relates to a crossbar switch controller (140) including an input terminal configured to receive a set of service request signals from a set of virtual output queues (602a-h) each comprising a set of packets, an arbiter including an arbitration pre-processor (604), arbitration post-processor (608) and arbiter controller, and an output terminal configured to receive a portion of the set of packets during an epoch. The arbiter pre-processor (694) is coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. The invention further includes an arbiter circuit (Fig. 4a) configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted.
摘要翻译：本发明涉及一种交叉开关控制器（140），其包括输入端子，该输入端子被配置为从包括一组分组的一组虚拟输出队列（602a-h）接收一组服务请求信号，仲裁器包括仲裁预处理处理器（604），仲裁后处理器（608）和仲裁器控制器，以及被配置为在历元期间接收该组分组的一部分的输出终端。仲裁预处理器（694）耦合到输入端并且被配置为以矩阵的形式表示服务请求信号集合，其中每个服务请求信号由行位置M和列位置N描述。发明还包括仲裁器电路（图4a），其被配置为在时代期间迭代地扫描矩阵，并向虚拟输出队列发出一组授权信号，以确定哪些服务请求被授予。

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