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1. 发明申请

WO2013020105A3 LOW-COST TRACKING SYSTEM 审中-公开
标题翻译：低成本跟踪系统
公开(公告)号：WO2013020105A3
公开(公告)日：2013-05-02
申请号：PCT/US2012049633
申请日：2012-08-03
申请人： RAMBUS INC , WARE FREDERICK A , ARYANFAR FARSHID , BROOKS JOHN WELSFORD
发明人： WARE FREDERICK A , ARYANFAR FARSHID , BROOKS JOHN WELSFORD
IPC分类号： G01S1/02 , G01S5/02
CPC分类号： G01S13/84 , G01S5/0294 , G01S5/06 , G01S7/52004 , G01S13/878 , G01S2007/4091
摘要： A method of tracking a second electronic device with respect to a first electronic device is disclosed. The method includes transmitting a first waveform of a first frequency along a first fixed path associated with the first device. A second waveform having a frequency based on the first frequency is wirelessly transmitted from the first device to the second device along a first wireless path. The second waveform is wirelessly transmitted from the second device to the first device along a second wireless path. The first and second waveforms are received at the phase comparator circuit. A first phase relationship of the received first waveform is then compared to a second phase relationship of the received re-transmitted waveform. A coordinate of the second device is determined with respect to a reference coordinate based on the comparing.
摘要翻译：公开了一种关于第一电子设备跟踪第二电子设备的方法。该方法包括沿着与第一设备相关联的第一固定路径传送第一频率的第一波形。具有基于第一频率的频率的第二波形沿着第一无线路径从第一设备无线传输到第二设备。沿着第二无线路径将第二波形从第二设备无线传输到第一设备。第一和第二波形在相位比较器电路处被接收。然后将所接收的第一波形的第一相位关系与所接收的重传波形的第二相位关系进行比较。基于比较关于参考坐标来确定第二设备的坐标。

2. 发明申请

WO2013009442A3 DYNAMICALLY CHANGING DATA ACCESS BANDWIDTH BY SELECTIVELY ENABLING AND DISABLING DATA LINKS 审中-公开
标题翻译：通过选择性地启用和禁用数据链接动态更改数据访问带宽
公开(公告)号：WO2013009442A3
公开(公告)日：2013-03-14
申请号：PCT/US2012043258
申请日：2012-06-20
申请人： RAMBUS INC , WARE FREDERICK A
发明人： WARE FREDERICK A
IPC分类号： G06F13/14 , G06F13/16 , G06F13/38
CPC分类号： G06F1/3287 , G06F1/3253 , G06F1/3278 , G06F1/3293 , G06F13/1694 , Y02D10/151 , Y02D10/157
摘要： Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.
摘要翻译：设备间信息传输的带宽会动态改变，以适应系统中采用的功率模式之间的转换。通过选择性地启用和禁用携带信息的单独控制链路和数据链路来改变带宽。在系统的最高带宽模式期间，所有的数据和控制链路都能够在整个过程中提供最大的信息。在系统的一个或多个较低带宽模式期间，禁用至少一个数据链路和/或至少一个控制链路以降低设备的功耗。在每个低带宽模式期间保持启用至少一个数据链路和至少一个控制链路。对于这些链路，相同的信令速率用于两种带宽模式，以减少否则将由信令速率改变引起的延迟。此外，还会为禁用的链接生成校准信息，以便这些链接可以快速重新投入使用。

3. 发明申请

WO2012021380A2 FAST-WAKE MEMORY 审中-公开
标题翻译：快速存储器
公开(公告)号：WO2012021380A2
公开(公告)日：2012-02-16
申请号：PCT/US2011046669
申请日：2011-08-04
申请人： RAMBUS INC , WARE FREDERICK A , ZERBE JARED L , LEIBOWITZ BRIAN S
发明人： WARE FREDERICK A , ZERBE JARED L , LEIBOWITZ BRIAN S
IPC分类号： G11C7/22 , G06F12/00 , G06F13/16 , G11C7/10
CPC分类号： G06F1/3275 , G06F1/324 , G06F3/0625 , G06F3/0659 , G06F3/0673 , G06F2213/0038 , G11C5/14 , G11C5/148 , G11C7/04 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C11/4076 , G11C2207/2227 , G11C2207/2254
摘要： One or more timing signals used to time data and command transmission over highspeed data and command signaling links are paused or otherwise disabled when a memory system enters a low-power state, and require substantial time to be re-established at appropriate frequency and/or phase as the system returns to an active operating state. Instead of waiting for the high-speed timing signals to be re-established before beginning memory access operations, an alternative, lower-frequency timing source is used to time transfer of one or more memory-access commands over a combination of data and command signaling links while the high-speed timing signals are being restored, thereby hastening transmission of memory-access commands to memory devices and reducing the incremental latency required to exit the low-power state. A timing signal generators capable of glitchlessly shifting a timing signal between two or more oscillation frequencies may also (or alternatively) be provided, thus enabling different- frequency timing signals to be delivered to system components via the same timing signal paths in either operating state. When the timing signal is used to time data (or command) transfer over information-bearing signaling links, the ability to glitchlessly shift the timing signal frequency enables a corresponding glitchless shift between lower and higher data rates on the information-bearing signaling links.
摘要翻译：当存储器系统进入低功率状态并且需要大量时间以适当的频率重新建立时，用于对高速数据和命令信令链路上的数据和命令传输进行计时的一个或多个定时信号被暂停或以其他方式禁用和/或阶段，因为系统返回到活动的操作状态。代替在开始存储器访问操作之前等待高速定时信号被重新建立，替代的较低频率的定时源被用于通过数据和命令信令的组合来定时传送一个或多个存储器访问命令而高速定时信号正在恢复，从而加快了对存储器设备的存储器访问命令的传输，并减少了退出低功耗状态所需的增量等待时间。也可以（或者替代地）提供能够在两个或更多个振荡频率之间无故障地移位定时信号的定时信号发生器，从而使得不同频率定时信号能够在任一操作状态下经由相同定时信号路径被传送到系统组件。当使用定时信号来对通过信息承载的信令链路进行数据（或命令）传输时，无信号地改变定时信号频率的能力使信息承载信令链路上的较低和较高数据速率之间的相应无毛刺移位成为可能。

4. 发明申请

WO2010098901A3 SYNTHETIC PULSE GENERATOR FOR REDUCING SUPPLY NOISE 审中-公开
标题翻译：用于减少供应噪声的合成脉冲发生器
公开(公告)号：WO2010098901A3
公开(公告)日：2010-10-21
申请号：PCT/US2010021024
申请日：2010-01-14
申请人： RAMBUS INC , WARE FREDERICK A
发明人： WARE FREDERICK A
IPC分类号： H03K19/0175 , H04L25/02
CPC分类号： H03K19/017581 , H03K19/017509 , H04L25/0272
摘要： A source-terminated transmitter conveys digital signals over a short channel as a voltage signal that transitions between levels for each symbol transition. The transmitter produces each transition by issuing a charge pulse onto the channel, and thus creates a series of charge pulses. The number of charge pulses per unit time is proportional to the transition density of the signal, as no charge pulse is required between like symbols. The supply current used to deliver the pulses is therefore dependent upon the data pattern. This data dependency can induce supply fluctuations, which can in turn cause errors and otherwise reduce performance. The transmitter issues a synthetic charge pulse for each adjacent pair of like symbols to reduce the data dependency of the supply current. The synthetic pulses can be scaled to match the charge required for symbol transitions on a given channel.
摘要翻译：源终端发射机通过短信道传送数字信号作为每个符号转换的电平之间转换的电压信号。发射机通过向通道发出充电脉冲来产生每个转换，从而产生一系列充电脉冲。每单位时间的充电脉冲数与信号的转换密度成比例，因为在相似符号之间不需要电荷脉冲。因此，用于传送脉冲的电源电流取决于数据模式。这种数据依赖性可能会导致电源波动，从而导致错误，从而降低性能。发射机为每个相邻的相似符号对发出合成充电脉冲，以减少电源电流的数据依赖性。可以缩放合成脉冲以匹配给定通道上符号转换所需的电荷。

5. 发明申请

WO2008130703A8 CLOCK SYNCHRONIZATION IN A MEMORY SYSTEM 审中-公开
标题翻译：记忆系统中的时钟同步
公开(公告)号：WO2008130703A8
公开(公告)日：2009-11-26
申请号：PCT/US2008005135
申请日：2008-04-18
申请人： RAMBUS INC , KIZER JADE M , WILSON JOHN M , EBLE JOHN III , WARE FREDERICK A
发明人： KIZER JADE M , WILSON JOHN M , EBLE JOHN III , WARE FREDERICK A
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according to a local clock signal 71/73. Based on ' the results of the sampling, the data strobe and local clock signal are synchronized. In this manner, the data is synchronized to the local clock signal so that sampling of data at the data destination can be performed according to the local clock signal rather than the data strobe.
摘要翻译：用于同步选通存储器系统10的系统和方法。在存储器读取和/或存储器写入操作期间，根据本地时钟信号71/73在数据目的地50/55处对相应的数据选通进行采样。基于“采样结果，数据选通和本地时钟信号同步。以这种方式，数据与本地时钟信号同步，使得可以根据本地时钟信号而不是数据选通来执行数据目的地的数据采样。

6. 发明申请

WO2012064638A3 MEMORY ACCESS DURING MEMORY CALIBRATION 审中-公开
标题翻译：存储器校准期间的存储器访问
公开(公告)号：WO2012064638A3
公开(公告)日：2012-08-16
申请号：PCT/US2011059550
申请日：2011-11-07
申请人： RAMBUS INC , SHAEFFER IAN , WARE FREDERICK A
发明人： SHAEFFER IAN , WARE FREDERICK A
IPC分类号： G06F13/14 , G06F12/00 , G06F13/38
CPC分类号： G06F12/1458 , G06F12/023 , G06F13/16 , G06F13/1657 , G06F13/1684 , G06F13/1694 , G06F2212/1044 , G06F2212/1052
摘要： A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.
摘要翻译：一种多列存储器系统，其中在存储器控制器和一列存储器之间执行校准操作，同时在控制器和其他存储器列之间传输数据。存储器控制器执行校准操作，该校准操作校准与存储器控制器和第一存储器中的存储器设备之间的第一数据总线有关的数据传输有关的参数。当控制器执行校准操作时，控制器还通过第二数据总线与第二存储器中的存储器设备传送数据。

7. 发明申请

WO2012033662A3 MEMORY CONTROLLER AND METHOD FOR TUNED ADDRESS MAPPING 审中-公开
标题翻译：用于调谐地址映射的存储器控制器和方法
公开(公告)号：WO2012033662A3
公开(公告)日：2012-05-31
申请号：PCT/US2011049510
申请日：2011-08-29
申请人： RAMBUS INC , WARE FREDERICK A
发明人： WARE FREDERICK A
IPC分类号： G06F12/06 , G06F12/02 , G11C7/22
CPC分类号： G06F12/10 , G06F12/0292 , G06F12/04 , Y02D10/13
摘要： A memory system maps physical addresses to device addresses in a way that reduces power consumption. The system includes circuitry for deriving efficiency measures for memory usage and selects from among various address-mapping schemes to improve efficiency. The address-mapping schemes can be tailored for a given memory configuration or a specific mixture of active applications or application threads. Schemes tailored for a given mixture of applications or application threads can be applied each time the given mixture is executing, and can be updated for further optimization. Some embodiments mimic the presence of an interfering thread to spread memory addresses across available banks, and thereby reduce the likelihood of interference by later- introduced threads.
摘要翻译：存储系统以减少功耗的方式将物理地址映射到设备地址。该系统包括用于导出用于存储器使用的效率测量的电路，并且从各种地址映射方案中进行选择以提高效率。可以针对给定的存储器配置或活动应用或应用程序线程的特定混合来定制地址映射方案。可以在每次给定混合物执行时为应用程序或应用程序线程定制的方案，并且可以更新以进一步优化。一些实施例模拟存在干扰线程以在可用存储体之间扩展存储器地址，从而降低稍后引入的线程的干扰的可能性。

8. 发明申请

WO2011062825A2 BIT-REPLACEMENT TECHNIQUE FOR DRAM ERROR CORRECTION 审中-公开
标题翻译： DRAM误差校正的位置更换技术
公开(公告)号：WO2011062825A2
公开(公告)日：2011-05-26
申请号：PCT/US2010056217
申请日：2010-11-10
申请人： RAMBUS INC , WARE FREDERICK A , TSERN ELY , VOGELSANG THOMAS
发明人： WARE FREDERICK A , TSERN ELY , VOGELSANG THOMAS
IPC分类号： G11C29/42 , G06F11/10 , G11C11/40 , G11C29/18
CPC分类号： G11C29/50016 , G06F11/1064 , G11C11/401 , G11C29/808
摘要： The disclosed embodiments provide a dynamic memory device, comprising a set of dynamic memory cells and a set of replacement dynamic memory cells. The set of replacement dynamic memory cells includes data cells which contain replacement data bits for predetermined faulty cells in the set of dynamic memory cells, and address cells which contain address bits identifying the faulty cells, wherein each data cell is associated with a group of address cells that identify an associated faulty cell in the set of dynamic memory cells. The dynamic memory device also includes a remapping circuit, which remaps a faulty cell in the set of dynamic memory cells to an associated replacement cell in the set of replacement cells.
摘要翻译：所公开的实施例提供了一种动态存储器设备，其包括一组动态存储器单元和一组替代动态存储器单元。替换动态存储单元组包括包含用于动态存储单元组中的预定故障单元的替换数据位的数据单元以及包含识别故障单元的地址位的地址单元，其中每个数据单元与一组地址这些单元识别该组动态存储器单元中的相关故障单元。动态存储设备还包括重新映射电路，其将动态存储单元组中的故障单元重新映射到替换单元组中的相关替换单元。

9. 发明申请

WO2010083073A3 PROTOCOL INCLUDING TIMING CALIBRATION BETWEEN MEMORY REQUEST AND DATA TRANSFER 审中-公开
标题翻译：协议包括存储器请求和数据传输之间的时序校准
公开(公告)号：WO2010083073A3
公开(公告)日：2010-10-21
申请号：PCT/US2010020135
申请日：2010-01-05
申请人： RAMBUS INC , WARE FREDERICK A , JESSUP HOLDEN
发明人： WARE FREDERICK A , JESSUP HOLDEN
IPC分类号： G06F13/16 , G06F1/04 , G06F1/30 , G06F9/06
CPC分类号： G06F13/1689
摘要： The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.
摘要翻译：所描述的实施例提供了一种用于由存储器控制器控制集成电路存储器件的系统。在操作期间，系统使用第一链路从存储器控制器向存储器件发送存储器访问请求。在发送存储器访问请求之后，存储器控制器向存储器件发送指定执行第二链路的定时校准操作的命令。系统随后使用第二链路传送与存储器访问请求相关联的数据，其中定时校准操作在发送存储器访问请求和传送与存储器访问请求相关联的数据之间发生。

10. 发明申请

WO2010065290A3 MEMORY SYSTEM WITH COMMAND FILTERING 审中-公开
标题翻译：具有指令过滤的存储器系统
公开(公告)号：WO2010065290A3
公开(公告)日：2010-08-19
申请号：PCT/US2009064813
申请日：2009-11-17
申请人： RAMBUS INC , WARE FREDERICK A , RICHARDSON WAYNE , KASAMSETTY KISHORE
发明人： WARE FREDERICK A , RICHARDSON WAYNE , KASAMSETTY KISHORE
IPC分类号： G06F13/32 , G06F11/10 , G06F12/00 , G06F13/24
CPC分类号： G11C29/56 , G01R31/3171 , G11C29/028 , G11C29/48 , G11C29/50012 , G11C29/56012
摘要： A memory system includes a memory controller coupled to at least one memory device via high-speed data and request links. The timing and voltage margins of the links are periodically calibrated to reduce bit error. The high-speed request links complicate calibration because commands issued over the uncalibrated request links can be erroneously interpreted by the memory device. Misinterpreted commands can disrupt the calibration procedure (e.g., a write command might be misinterpreted as a power-down command). The memory controller addresses this problem using a separate, low-speed control interface to issue a filter command that instructs the memory device to decline potentially disruptive requests when in a calibration mode.
摘要翻译：存储器系统包括经由高速数据和请求链路耦合到至少一个存储器设备的存储器控制器。链路的定时和电压裕度被定期校准，以减少位误差。高速请求链接使校准变得复杂，因为通过未校准的请求链接发出的命令可能被存储器件错误地解释。错误解释的命令可能会中断校准过程（例如，写命令可能被误解为掉电命令）。存储器控制器使用单独的低速控制接口来解决这个问题，发出一个过滤器命令，指示当处于校准模式时存储器件可能会破坏潜在的破坏性请求。

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