专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO1998028747A1 MEMORY AND METHOD FOR SENSING SUB-GROUPS OF MEMORY ELEMENTS 审中-公开
标题翻译：用于感测存储元件子组的记忆和方法
公开(公告)号：WO1998028747A1
公开(公告)日：1998-07-02
申请号：PCT/US1997023076
申请日：1997-12-15
申请人： RAMBUS, INC.
发明人： RAMBUS, INC. , BARTH, Richard, M. , STARK, Donald, C. , LAI, Lawrence , RICHARDSON, Wayne, S.
IPC分类号： G11C08/00
CPC分类号： G11C7/06 , G11C8/14 , G11C11/4085 , G11C11/4091
摘要： A memory and method of operation is described. In one embodiment, the memory includes a group of memory cells divided into a plurality of sub-groups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a sub-group and is coupled to the memory cells in the row of the corresponding sub-group: Sense amplifier circuitry is coupled to the group of memory cells. The sense amplifier circuitry is divided into a plurality of sub-sensing circuits, each of the plurality of sub-sensing circuits selectively coupled to a corresponding one of the plurality of sub-groups. The memory includes a control mechanism to control the word lines and sub-sensing circuit(s) that are activated at any one time such that only those sub-word lines and sub-sensing circuits needed to perform memory operations are operated and consume power. In an alternate embodiment, the control mechanism controls the sub-word lines and sub-sensing circuits to enable substantially concurrent access to different sub-groups of memory cells from different rows of the memory.
摘要翻译：描述了存储器和操作方法。在一个实施例中，存储器包括分成多个子组的一组存储器单元。子字线选择性地耦合到主字线，每个子字线对应于一个子组，并且被耦合到相应子组的行中的存储器单元：感测放大器电路耦合到该组存储器细胞。感测放大器电路被分成多个子感测电路，多个子感测电路中的每一个选择性地耦合到多个子组中的相应一个子组。存储器包括控制机构，用于控制在任何一个时间被激活的字线和子感测电路，使得只需要执行存储器操作所需的那些子字线和子感测电路并消耗功率。在替代实施例中，控制机构控制子字线和子感测电路以使得能够从存储器的不同行实质上并发地访问存储器单元的不同子组。

2. 发明申请

WO1994029871A1 METHOD AND APPARATUS FOR WRITING TO MEMORY COMPONENTS 审中-公开
标题翻译：用于写入存储器组件的方法和装置
公开(公告)号：WO1994029871A1
公开(公告)日：1994-12-22
申请号：PCT/US1994006157
申请日：1994-06-01
申请人： RAMBUS, INC.
发明人： RAMBUS, INC. , WARE, Frederick, A. , DILLON, John, B. , BARTH, Richard, M. , GARRETT, Billy, Wayne, Jr. , ATWOOD, John, Girdner, Jr. , FARMWALD, Michael, P. , CRISP, Richard, DeWitt
IPC分类号： G11C07/00
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/103 , G11C7/1045 , G11C7/1078 , G11C7/1087
摘要： In the memory system of the present invention, additional operating modes are provided to enhance the functionality and performance of the memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.
摘要翻译：在本发明的存储器系统中，提供附加的操作模式以增强存储器系统的功能和性能。在一个实施例中，向每个列访问中使用的写入数据提供唯一的位掩码。在替代实施例中，提供位掩码寄存器和字节掩码寄存器以支持位电平和字节电平掩蔽。位掩码和写数据寄存器被实现为单个寄存器，以提供功能，同时最小化组件空间和成本。在另一个实施例中，提供单独的位掩码和字节掩码。字节掩码在一个周期内加载掩码数据，并在下一个“q”列写入访问期间使用。该结构提供无位掩蔽的操作模式，每行访问提供位掩码，并提供每列访问的位掩码。为了增强诸如二维图形系统的系统的功能，在替代实施例中，存储器系统具有两个寄存器和选择控制线，以从两个寄存器之一中选择数据。在计算机图形系统中，用于在前景和背景颜色之间进行选择。该实施例可以与所描述的其他实施例一起使用以提供增强的功能和性能。

3. 发明申请

WO1998029874A1 METHOD AND APPARATUS FOR SHARING SENSE AMPLIFIERS BETWEEN MEMORY BANKS 审中-公开
标题翻译：用于在存储器之间共享感知放大器的方法和装置
公开(公告)号：WO1998029874A1
公开(公告)日：1998-07-09
申请号：PCT/US1997023106
申请日：1997-12-17
申请人： RAMBUS, INC.
发明人： RAMBUS, INC. , BARTH, Richard, M. , STARK, Donald, C. , TSERN, Ely, K.
IPC分类号： G11C07/00
CPC分类号： G11C7/06 , G11C7/00 , G11C11/409
摘要： A memory device includes a first memory bank and a second memory bank, each memory bank having at least one subarray of memory cells. Multiple sense amplifiers are coupled to both the first memory bank and the second memory bank. The multiple sense amplifiers are configured for use by both the first memory bank and the second memory bank, but not simultaneously. A control mechanism is used to avoid accessing the first memory bank and the second memory bank simultaneously. The sharing of sense amplifiers between memory banks minimizes the die area penalty caused by additional memory banks.
摘要翻译：存储器件包括第一存储体和第二存储体，每个存储体具有至少一个存储单元的子阵列。多感测放大器耦合到第一存储体和第二存储体两者。多个读出放大器被配置为由第一存储器组和第二存储器组使用，但不能同时使用。使用控制机制来避免同时访问第一存储体和第二存储体。存储器组之间的读出放大器的共享使由附加存储体引起的管芯面积损失最小化。

4. 发明申请

WO1997042557A2 ASYNCHRONOUS REQUEST/SYNCHRONOUS DATA DYNAMIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：异步请求/同步数据动态随机存取
公开(公告)号：WO1997042557A2
公开(公告)日：1997-11-13
申请号：PCT/US1997007463
申请日：1997-05-01
申请人： RAMBUS, INC.
发明人： RAMBUS, INC. , BARTH, Richard, M. , HOROWITZ, Mark, A. , HAMPEL, Craig, E. , WARE, Frederick, A.
IPC分类号： G06F00/00
CPC分类号： G11C7/222 , G06F13/16 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C8/18 , Y02D10/14
摘要： A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.
摘要翻译：提供了一种用于在计算机系统内传送信息的方法和系统。该系统包括具有较低功率模式的存储器件，其中数据传输电路不由时钟信号驱动，并且其中数据传输电路由时钟信号驱动的较高功率模式。该系统还包括存储器控制器，其向控制信号发送控制信号以发起数据传输交易。存储器装置异步地接收控制信号，并且响应于一个控制信号而呈现第二模式。当存储器件处于第二模式时，存储器控制器发送控制信号以识别特定的时钟周期。存储设备同步传输数据。存储器件基于所识别的时钟周期和指定的数据传输的类型确定何时开始数据传输。

5. 发明申请

WO1994028550A1 DYNAMIC RANDOM ACCESS MEMORY SYSTEM 审中-公开
标题翻译：动态随机存取系统
公开(公告)号：WO1994028550A1
公开(公告)日：1994-12-08
申请号：PCT/US1994005798
申请日：1994-05-23
申请人： RAMBUS, INC.
发明人： RAMBUS, INC. , WARE, Frederick, A. , DILLON, John, B. , BARTH, Richard, M. , GARRETT, Billy, Wayne, Jr. , ATWOOD, John, Girdner, Jr. , FARMWALD, Michael, P.
IPC分类号： G11C05/06
CPC分类号： G11C5/066
摘要： As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.
摘要翻译：随着与DRAM的接口变得越来越先进和更高的性能，支持接口所需的接口和信号线变得越来越昂贵。因此，为了利用接口中的信号线的高性能，期望使信号线的数量最小化并且使与DRAM接口的信号线的带宽最大化。在本发明的DRAM存储器系统中，地址和控制线被组合，信息被多路复用，使得DRAM引脚始终具有大致相同的信息速率。

6. 发明申请

WO1994028477A1 METHOD AND APPARATUS FOR POWER CONTROL IN DEVICES 审中-公开
标题翻译：用于设备功率控制的方法和装置
公开(公告)号：WO1994028477A1
公开(公告)日：1994-12-08
申请号：PCT/US1994005311
申请日：1994-05-13
申请人： RAMBUS, INC.
发明人： RAMBUS, INC. , WARE, Frederick, A. , GASBARRO, James, A. , DILLON, John, B. , GRIFFIN, Matthew, M. , BARTH, Richard, M. , HOROWITZ, Mark, A.
IPC分类号： G06F01/32
CPC分类号： G11C5/14
摘要： A power control circuit to minimize power consumption of CMOS circuits by disabling/enabling the clock input to the CMOS circuit. A phase locked loop (PLL) or delay locked loop (DLL) drives a capacitive load of the component and a dummy load comparable to the component load. A standby latch is provided to control the clock input to the component. In a standby state, the clock signal is not provided to the component but the PLL/DLL continues to operate, driving the dummy load. Thus, when it is desirable to power on the circuit, the standby latch is reset and the clock signal is provided to the component, thereby turning on the component with little latency.
摘要翻译：电源控制电路，通过禁止/使能CMOS电路的时钟输入来最小化CMOS电路的功耗。锁相环（PLL）或延迟锁定环（DLL）驱动组件的容性负载和与组件负载相当的虚拟负载。提供备用锁存器来控制对组件的时钟输入。在待机状态下，时钟信号不提供给组件，但PLL / DLL继续运行，驱动虚拟负载。因此，当期望对电路通电时，备用锁存器被复位，并且时钟信号被提供给部件，从而以小的延迟打开部件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式