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1. 发明申请

WO2005125130A2 COMMUNICATION CHANNEL CALIBRATION USING FEEDBACK 审中-公开
标题翻译：使用反馈通信通道校准
公开(公告)号：WO2005125130A2
公开(公告)日：2005-12-29
申请号：PCT/US2005/020208
申请日：2005-06-08
申请人： RAMBUS, INC. , KIM, Jun , RICHARDSON, Wayne, S. , CHIU, Glenn
发明人： KIM, Jun , RICHARDSON, Wayne, S. , CHIU, Glenn
IPC分类号： H04L12/56
CPC分类号： H04B17/11 , H04L5/1438 , H04L25/03343 , H04L2025/03802
摘要： A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.
摘要翻译：用于校准耦合第一和第二组件的通信信道的方法包括在第二组件上传输数据信号从第一分量到通信信道上的第二分量，以及感测数据信号的相位等特性。关于感测到的特性的信息使用辅助信道反馈到第一分量。响应于该信息，在第一组件上调整用于发射机的可调参数，例如相位。而且，感测从第二组件上的发射机接收到的数据信号的特性，并用于调整第一组件上的接收机的可调参数。

2. 发明申请

WO2008153645A2 ADJUSTING CLOCK ERROR ACROSS A CIRCUIT INTERFACE 审中-公开
标题翻译：通过电路接口调整时钟错误
公开(公告)号：WO2008153645A2
公开(公告)日：2008-12-18
申请号：PCT/US2008/005858
申请日：2008-05-02
申请人： RAMBUS, INC. , CHIU, Glenn
发明人： CHIU, Glenn
IPC分类号： H03L1/00
CPC分类号： G11C7/1072 , G11C7/222 , G11C2207/2254
摘要： A system is provided with clock skew measurement and correction technology. A first circuit or memory controller 4 includes measuring circuits to measure relative timing or phase offsets of multiple clock signals of a second circuit or memory 6. One measuring circuit is configured for incremental changing of the phase of a transmitted test data sequence to measure and correct timing of a memory receiver circuit's quadrature clocks based on results of a data comparison of transmitted and received test data. Another measuring circuit is configured to scan a received test data sequence for data transitions to measure and correct timing of a memory transmitter circuit ' s quadrature clocks based on spacing or timing between detected transitions. Individual memory clock generators 30 are controlled with adjustable delay circuits 47 for changing phase of different clock signals of the memory to set the clock signals based on the measurements of the controller.
摘要翻译：系统提供时钟偏差测量和校正技术。第一电路或存储器控制器4包括用于测量第二电路或存储器6的多个时钟信号的相对定时或相位偏移的测量电路。一个测量电路被配置为用于逐渐改变发送的测试数据序列的相位以测量和校正基于发送和接收的测试数据的数据比较的结果，存储器接收器电路的正交时钟的定时。另一测量电路被配置为扫描接收到的测试数据序列用于数据转换，以基于检测到的转换之间的间隔或定时来测量和校正存储器发射器电路的正交时钟的定时。单个存储器时钟发生器30由可调延迟电路47控制，用于改变存储器的不同时钟信号的相位，以基于控制器的测量值设置时钟信号。

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