专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO1998027482A1 METHOD AND APPARATUS FOR SUPPORTING POWER CONSERVATION OPERATION MODES 审中-公开
标题翻译：支持节电运行模式的方法和装置
公开(公告)号：WO1998027482A1
公开(公告)日：1998-06-25
申请号：PCT/US1997021246
申请日：1997-11-18
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , JACKSON, David, R. , CROSS, Leonard, W. , JACOBS, Robert, A. , OZTASKIN, Ali, S.
IPC分类号： G06F01/32
CPC分类号： G06F1/3237 , G06F1/08 , G06F1/32 , G06F1/325 , Y02D10/128
摘要： An apparatus for managing power in an electronic device that receives the power from a bus is described. The apparatus comprises a clock enable circuit that disables a clock (430) that generates nominal clock frequencies derived from raw frequencies output by an oscillator upon receiving a first signal. A time-wise independent time reference circuit (420) is coupled to the clock enable circuit (430). The time-wise independent time reference circuit (420) sends the first signal to the clock enable circuit (430) a first predetermined period of time after receiving a signal to enter into a suspend state.
摘要翻译：描述了一种用于管理从总线接收电力的电子装置中的电力的装置。该装置包括时钟使能电路，其禁用产生从收到第一信号时由振荡器输出的原始频率导出的标称时钟频率的时钟（430）。时间独立的时间参考电路（420）耦合到时钟使能电路（430）。时间独立时间参考电路（420）在接收到进入暂停状态的信号之后的第一预定时间段内将第一信号发送到时钟使能电路（430）。

2. 发明申请

WO1997035246A1 MICROCONTROLLER WITH AUTO-ALARM DEVICE 审中-公开
标题翻译：微控制器SELBSTWECKVORRICHTUNG
公开(公告)号：WO1997035246A1
公开(公告)日：1997-09-25
申请号：PCT/DE1997000553
申请日：1997-03-19
申请人： ROBERT BOSCH GMBH , AAB, Volker
发明人： ROBERT BOSCH GMBH
IPC分类号： G06F01/32
CPC分类号： G06F1/324 , B60R16/0315 , G06F1/3203 , G06F1/3287 , Y02D10/126 , Y02D10/171
摘要： A microcontroller with a self-prompting (self-wake-up) device, particularly for use in electrical adjusting drives, having a control device for specifying an active and an inactive operating state to economize on supply power, contains an oscillator for emitting a prompting signal or a clock frequency. This oscillator is a low-frequency, power-saving oscillator. Provided in the microcontroller is a circuit, preferably a disconnectible phase-locking loop, which, from the low frequency of the oscillator, generates a substantially higher clock frequency for microcontroller core. The low-frequency oscillator is also integrated as an original component into the microcontroller. An undervoltage detection, whose output signal is able to be supplied directly to the microcontroller core, indicates undervoltage conditions immediately. Using a time-switch logic which monitors a non-operative time of the microcontroller core, the core is activated again via a prompting circuit. In the case of certain functions, it is also possible to work in a power-saving manner solely with the low frequency. Thus, a necessary buffer capacitance can be smaller.

3. 发明申请

WO1993012480A1 APPARATUS FOR REDUCING COMPUTER SYSTEM POWER CONSUMPTION 审中-公开
标题翻译：降低计算机系统功耗的装置
公开(公告)号：WO1993012480A1
公开(公告)日：1993-06-24
申请号：PCT/US1992010798
申请日：1992-12-14
申请人： COMPAQ COMPUTER CORPORATION
发明人： COMPAQ COMPUTER CORPORATION , ATKINSON, Lee, W.
IPC分类号： G06F01/32
CPC分类号： G06F1/3215 , G06F1/3203 , G06F11/3409 , G06F11/3423 , G06F12/0802 , G06F2201/86 , G06F2201/88 , G06F2201/885 , Y02D10/126 , Y02D10/34
摘要： A battery powered computer system determines when the system is not in use by monitoring various events associated with the operation of the system. The system preferably monitors the number of cache read misses and write operations, i.e., the cache hit rate, and reduces the system clock frequency when the cache hit rate rises above a certain level. When the cache hit rate is above a certain level, then it can be assumed that the processor is executing a tight loop, such as when the processor is waiting for a key to be pressed and then the frequency can be reduced without affecting system performance. Alternatively, the apparatus monitors the occurrence of memory page misses, I/O write cycles or other events to determine the level of activity of the computer system.
摘要翻译：电池供电的计算机系统通过监视与系统的操作相关联的各种事件来确定系统何时未使用。该系统优选地监视高速缓存读取未命中和写入操作的数量，即，高速缓存命中率，并且当高速缓存命中率上升到高于某一水平时，降低系统时钟频率。当高速缓存命中率高于一定水平时，可以假设处理器正在执行紧密循环，例如当处理器正在等待一个按键被按下时，可以在不影响系统性能的情况下降低频率。或者，该装置监视存储器页面未命中，I / O写入周期或其他事件的发生，以确定计算机系统的活动级别。

4. 发明申请

WO1991002303A1 WAKE-UP CIRCUIT ARRANGEMENT FOR A MICROPROCESSOR 审中-公开
标题翻译：微处理器的唤醒电路布置
公开(公告)号：WO1991002303A1
公开(公告)日：1991-02-21
申请号：PCT/DE1990000565
申请日：1990-07-25
申请人： ROBERT BOSCH GMBH , ARNOLD, Karl-Heinz
发明人： ROBERT BOSCH GMBH
IPC分类号： G06F01/32
CPC分类号： G06F1/3215 , B60R16/0315 , G06F1/325
摘要： In a wake-up circuit arrangement for a microprocessor ( mu C) which controls electrical devices, in particular in a motor vehicle, peripheral components (15, 17) of the microprocessor ( mu C) can be disconnected fron a voltage supply arrangement (7) and the microprocessor ( mu C) can be switched into an idle or stop mode. In order to execute a queueing program, the microprocessor ( mu C) can be switched out of this mode into its operating mode by an external switching signal which actuates an electronic wake-up circuit (20, 20') associated with the microprocessor ( mu C). To ensure reliable switching of the microprocessor ( mu C) independently of the type and duration of the control signal, the switching signals are fed in the form of potential jumps to a timing pulse generator stage (C1, R8, IC1) the output (23) of which switches a pulse (25) of defined length to the interrupt input (INT) of the microprocessor ( mu C). The microprocessor ( mu C) then exits the idle or stop mode and switches on the voltage supply arrangement (7) for the peripheral components (15, 17).
摘要翻译：在用于控制电气设备（特别是机动车辆）的微处理器（μC）的唤醒电路装置中，微处理器（μC）的外围部件（15,17）可以在电压供应装置（7））和微处理器（μC）可以切换到空闲或停止模式。为了执行排队程序，可以通过外部切换信号将微处理器（μC）从该模式切换到其运行模式，该外部切换信号致动与微处理器相关的电子唤醒电路（20,20'）（mu C）。为了确保微处理器的可靠切换（μC）独立于控制信号的类型和持续时间，开关信号以电位跳变的形式馈送到定时脉冲发生器级（C1，R8，IC1）的输出（23 ）将具有限定长度的脉冲（25）切换到微处理器的中断输入（INT）（μC）。微处理器（μC）然后退出空闲或停止模式并且接通周边组件（15,17）的电压供应装置（7）。

5. 发明申请

WO1991000565A2 POWER CONSERVATION IN MICROPROCESSOR CONTROLLED DEVICES 审中-公开
标题翻译：微处理器控制器件中的功率保存
公开(公告)号：WO1991000565A2
公开(公告)日：1991-01-10
申请号：PCT/US1990003466
申请日：1990-06-20
申请人： HAND HELD PRODUCTS, INC.
发明人： HAND HELD PRODUCTS, INC. , PERRY, Richard, A. , STANT, Vernon, L.
IPC分类号： G06F01/32
CPC分类号： G06F1/3293 , G06F1/08 , G06F1/3203 , Y02D10/122
摘要： Power may be conserved and battery life may be extended in a microprocessor controlled device by providing two microprocessors, one of which is a low power, low performance low speed processor for performing background tasks, the other of which is a high power, high performance, high speed processor for performing computationally intensive foreground tasks. The low speed processor activates the high speed processor when a high performance task is to be performed. When activating the high performance processor, the low performance processor also controls the device's power supply to provide high voltage to the high speed processor. The high speed processor may run at variable clock speeds, with power consumption of the processor increasing with increasing speed. The high speed processor selects its own clock speed based upon the task to be performed, by including a clock speed in each software subroutine which controls a task. The software subroutine associated with a task is thereby executed at its associated clock speed, which may be chosen to be the lowest possible clock speed consistent with the task to be performed.

6. 发明申请

WO1996041253A1 POWER DOWN MODE FOR COMPUTER SYSTEM 审中-公开
标题翻译：电脑系统关机模式
公开(公告)号：WO1996041253A1
公开(公告)日：1996-12-19
申请号：PCT/US1996009693
申请日：1996-06-07
申请人： S MOS SYSTEMS, INC.
发明人： S MOS SYSTEMS, INC. , HO, Simon
IPC分类号： G06F01/32
CPC分类号： G09G5/006 , G06F1/3218 , G06F1/3281 , G09G3/2025 , G09G3/3648 , G09G5/363 , G09G2330/021 , G09G2340/0428 , Y02D10/158 , Y02D50/20
摘要： A computer system includes a CPU and VGA/LCD controller interacting with a main system memory for processing input data and displaying it on an LCD panel screen that includes a plurality of row and column drive chips on the panel. Each column drive chip includes a panel driver memory and panel driver control logic. A frame rate modulated grey-scale data signal is fed from the processor and VGA/LCD controller to the panel driver memory. Timing signals, including horizontal and vertical clocks, and data shift signals, are fed to the panel driver control circuit to control the panel driver memory from which data is read out for display on the LCD panel screen. Upon detection of the absence of screen update information for two full frame periods, the system enters a power down mode by re-mapping the grey-scale data to black-and-white data, stopping the data shift clock, and disabling portions of the VGA/LCD controller and its sequencer so that the latter enters a screen off mode. Stopping of the data shift clock causes the display panel and its panel driver memory to enter a self-refresh mode in which a frame of data stored in the panel driver memory is repetitively read out under control of the vertical and horizontal clock signals.
摘要翻译：计算机系统包括与主系统存储器相互作用的CPU和VGA / LCD控制器，用于处理输入数据并将其显示在LCD面板屏幕上，该LCD面板屏幕包括面板上的多个列和列驱动芯片。每列驱动芯片包括面板驱动器存储器和面板驱动器控制逻辑。帧速调制灰度数据信号从处理器和VGA / LCD控制器馈送到面板驱动器存储器。定时信号（包括水平和垂直时钟）和数据移位信号被馈送到面板驱动器控制电路以控制面板驱动器存储器，从该数据读出数据被读出以在LCD面板屏幕上显示。当检测到两个全帧周期没有屏幕更新信息时，系统通过将灰度数据重新映射到黑白数据，停止数据移位时钟并禁止部分 VGA / LCD控制器及其音序器，使后者进入屏幕关闭模式。停止数据移位时钟使得显示面板及其面板驱动器存储器进入自刷新模式，其中存储在面板驱动器存储器中的数据帧在垂直和水平时钟信号的控制下重复读出。

7. 发明申请

WO1996041252A1 COMPUTER SYSTEM WITH VIDEO DISPLAY CONTROLLER HAVING POWER SAVING MODES 审中-公开
标题翻译：具有节电模式的视频显示控制器的计算机系统
公开(公告)号：WO1996041252A1
公开(公告)日：1996-12-19
申请号：PCT/US1996007452
申请日：1996-05-21
申请人： S MOS SYSTEMS, INC.
发明人： S MOS SYSTEMS, INC. , CHEE, Lawrence , TUCKER, David , CHENG, Brett , GILLETT, Kevin , BYSTRICKY, Juraj
IPC分类号： G06F01/32
CPC分类号： G06F1/3218 , G06F3/1431 , G09G3/3406 , G09G3/3611 , G09G5/366 , G09G2320/0606 , G09G2320/0626 , G09G2330/022 , G09G2340/0428
摘要： A computer system includes an operator input device, such as a keyboard or mouse device, a central processing unit (CPU) responding to an operator input by performing a processing function, and a display device, such as a liquid crystal display (LCD) or cathode ray tube (CRT) providing a visible image to the computer user as an output of computer activity. The computer system includes a video display controller (VDC) with a graphics generator. This VDC receives image information, such as text or graphics generated by the CPU, or retrieved by the CPU from another facility (such as a CD-ROM) of the computer system, and responsively provides image signals driving the CRT or LCD display. The VDC includes a power saving controller implementing one of several available power saving modes dependent upon one or more of several possible inputs. One of the inputs may be a watch dog timer monitoring computer activity and enabling a power saving mode when the timer times out. One or more of the inputs may be a hardware input (switch contact closure, for example), while another of the inputs may be a software input. Each of the power saving modes includes the same list of VDC functions which may individually be enabled or disabled in each power saving mode dependent upon a bit value entered into a register of the power saving controller. Each of the power saving modes is ranked with the others in an order of succession. Accordingly, when each mode of power saving is enabled, it disables the lower-ranked modes of power saving. In turn, each mode of power saving is disabled and succeeded if a higher-ranked mode is enabled.
摘要翻译：计算机系统包括诸如键盘或鼠标装置的操作者输入装置，通过执行处理功能来响应操作者输入的中央处理单元（CPU），以及诸如液晶显示器（LCD）或显示装置作为计算机活动的输出，向计算机用户提供可视图像的阴极射线管（CRT）。计算机系统包括具有图形生成器的视频显示控制器（VDC）。该VDC接收诸如由CPU生成的文本或图形的图像信息，或CPU从计算机系统的另一设施（例如CD-ROM）检索，并且响应地提供驱动CRT或LCD显示器的图像信号。 VDC包括一个功率节省控制器，其根据几个可能的输入中的一个或多个实现几种可用省电模式之一。其中一个输入可以是监视计时器活动的看门狗定时器，并且当定时器超时时启用省电模式。一个或多个输入可以是硬件输入（例如，开关触点闭合），而另一个输入可以是软件输入。每个省电模式包括相同的VDC功能列表，其可以在每个省电模式下单独地被启用或禁用，这取决于输入到节电控制器的寄存器中的位值。每个省电模式按其他顺序排列顺序。因此，当每个省电模式被使能时，它禁用较低级别的省电模式。反过来，如果启用了较高排名的模式，则每个省电模式被禁用并成功。

8. 发明申请

WO1996013768A1 ACTIVE POWER DOWN FOR PC CARD I/O APPLICATIONS 审中-公开
标题翻译： PC卡I / O应用的主动关机
公开(公告)号：WO1996013768A1
公开(公告)日：1996-05-09
申请号：PCT/US1995013884
申请日：1995-10-26
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , PIERCE, Michael, E. , SCHEER, David, C.
IPC分类号： G06F01/32
CPC分类号： G06F1/3215 , G05F1/575 , G06F1/325
摘要： A system for controlling the power consumption of an add-in PC card (10) operating within a host computer. The host computer includes a power supply (24) that provides all power used by the PC card (10). The PC card includes communication registers required for communication between the host computer and the PC card. The PC card also includes a microcontroller (26) connected to an I/O subsystem (32) and a multi-pin I/O connector (36). A first side of multi-pin I/O connector (36) is connected to the I/O subsystem and second side (38) is connected to a source of I/O signals external to the host computer. An external register module (16) is connected to the microcontroller (26) and communicates with the host computer. The external register module (16) contains the communication registers. A status detector located on the PC card (10) detects whether the I/O subsystem (32) is processing I/O information, and supplies a status signal indicative thereof. A power management module (68) is also located on the PC card (10) and is connected to the status connector. The power management module receives the status signal from the status detector and supplies one or more predetermined power levels as a result of the status signal.
摘要翻译：一种用于控制在主计算机内操作的附加PC卡（10）的功耗的系统。主计算机包括提供PC卡（10）使用的所有电力的电源（24）。 PC卡包括主计算机和PC卡之间通信所需的通信寄存器。 PC卡还包括连接到I / O子系统（32）和多针I / O连接器（36）的微控制器（26）。多引脚I / O连接器（36）的第一侧连接到I / O子系统，第二侧（38）连接到主计算机外部的I / O信号源。外部寄存器模块（16）连接到微控制器（26）并与主机通信。外部寄存器模块（16）包含通信寄存器。位于PC卡（10）上的状态检测器检测I / O子系统（32）是否正在处理I / O信息，并提供指示其的状态信号。电源管理模块（68）也位于PC卡（10）上，并连接到状态连接器。电源管理模块从状态检测器接收状态信号，并作为状态信号的结果提供一个或多个预定功率电平。

9. 发明申请

WO1995030950A1 METHOD AND APPARATUS FOR MAINTAINING A STATE OF A STATE MACHINE DURING UNSTABLE CLOCK CONDITIONS WITHOUT CLOCK DELAY 审中-公开
标题翻译：在没有时钟延迟的不稳定时钟条件下维护状态机的状态的方法和装置
公开(公告)号：WO1995030950A1
公开(公告)日：1995-11-16
申请号：PCT/US1995005649
申请日：1995-05-08
申请人： APPLE COMPUTER, INC.
发明人： APPLE COMPUTER, INC. , BAILEY, Robert, L. , JOHNSON, Mary, B.
IPC分类号： G06F01/32
CPC分类号： H03K5/1252 , G06F1/04 , G06F11/00
摘要： An apparatus and method for protecting the state of a state machine from an unstable clock signal. The apparatus of one embodiment includes a state register having an input and a first output which provides an output signal corresponding to the state of the state machine and a set or reset input coupled, through a logic circuit, to the first output. The logic circuit is coupled to receive a signal indicating the unstable state of the clock signal. The logic circuit feeds back the output from the first output to the set or reset input to maintain the state in the state register while the clock signal is unstable. An embodiment of the method comprises storing a state in a state register, receiving a first signal indicating an unstable state of the clock signal and feeding back the output from the state register to the set or reset input while the first signal indicates the unstable clock exits. In an alternative embodiment, the output from the state register is fed back to its input while the first signal indicates the unstable clock exits.
摘要翻译：一种用于保护状态机的状态不稳定的时钟信号的装置和方法。一个实施例的装置包括具有输入的状态寄存器和提供与状态机的状态相对应的输出信号的第一输出以及通过逻辑电路耦合到第一输出的置位或复位输入。逻辑电路被耦合以接收指示时钟信号的不稳定状态的信号。当时钟信号不稳定时，逻辑电路将输出从第一个输出反馈到设置或复位输入，以将状态保持在状态寄存器中。该方法的一个实施例包括将状态存储在状态寄存器中，接收指示时钟信号不稳定状态的第一信号，并将来自状态寄存器的输出反馈给设置或复位输入，同时第一信号指示不稳定时钟退出。在替代实施例中，来自状态寄存器的输出被反馈到其输入，而第一信号指示不稳定的时钟退出。

10. 发明申请

WO1993007558A1 POWER MANAGEMENT SYSTEM 审中-公开
标题翻译：电源管理系统
公开(公告)号：WO1993007558A1
公开(公告)日：1993-04-15
申请号：PCT/CA1992000441
申请日：1992-10-05
申请人： NATIONAL RESEARCH COUNCIL OF CANADA , TILLER, Dale, K. , KEMP, William, H. , SHIDDLER, Victor, J. , NEWSHAM, Guy, R.
发明人： NATIONAL RESEARCH COUNCIL OF CANADA
IPC分类号： G06F01/32
CPC分类号： G06F1/3209 , G06F1/266 , G06F1/325 , G06F1/3265 , G06F1/3284 , G06F2200/261 , Y02D10/153 , Y02D10/159 , Y02D10/175
摘要： A power management system for use in association with desktop computers and like equipment powered from a mains supply, comprises: a monitor for monitoring Input/Output activity on the computer; a device for generating a time-out signal due to the absence of Input/Output activity during a predetermined period of time; a device for storing user-selectable criteria determining the response of the system to said time-out signal; a device for generating a data signal at an external interface port of the desktop computer based on said stored criteria and the presence of the time-out signal; and an external power supply device, comprising a power inlet for connection to the mains supply, a plurality of power outlets for supplying power to the desktop computer and associated peripheral equipment, controllable switches associated with each power outlet for selectively connecting and disconneting the power supply thereto in response to a control signal, an interface connectable to the external interface port for receiving said data signal therethrough, and a processor responsive to the data signal to generate the control signals for the controllable switches associated with the power outlets in accordance with the stored user-selectable criteria. The system can result in substantial energy savings due to the reduction in wasted energy caused by computers being left on while unattended.
摘要翻译：用于与台式计算机相关的电力管理系统，以及由主电源供电的设备，包括：用于监视计算机上的输入/输出活动的监视器; 用于在预定时段内由于不存在输入/输出活动而产生超时信号的装置; 用于存储确定系统对所述超时信号的响应的用户可选标准的装置; 基于所述存储的标准和超时信号的存在，在台式计算机的外部接口端口处生成数据信号的装置; 以及外部电源装置，包括用于连接到电源的电源入口，用于向台式计算机和相关联的外围设备供电的多个电源插座，与每个电源插座相关联的可控开关，用于选择性地连接和断开电源其响应于控制信号，可连接到外部接口端口的接口，用于接收所述数据信号;以及处理器，响应于所述数据信号，根据所存储的数据信号产生与电源插座相关联的可控开关的控制信号用户可选择的标准。由于计算机在无人值守的情况下所引起的浪费能量的减少，该系统可以节省大量能源。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式