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1. 发明申请

WO2009079455A1 IMPROVING MEMORY READ STABILITY USING SELECTIVE PRECHARGE OF BIT LINE SECTIONS 审中-公开
标题翻译：使用选择性预置位线段来改善内存读取稳定性
公开(公告)号：WO2009079455A1
公开(公告)日：2009-06-25
申请号：PCT/US2008/086829
申请日：2008-12-15
申请人： QUALCOMM Incorporated , ABU-RAHMA, Mohamed H. , CHABA, Ritu , CHEN, Nan , YOON, Sei Seung
发明人： ABU-RAHMA, Mohamed H. , CHABA, Ritu , CHEN, Nan , YOON, Sei Seung
IPC分类号： G11C7/12
CPC分类号： G11C11/419 , G11C7/02 , G11C7/04 , G11C7/12 , G11C7/18 , G11C2207/002
摘要： A memory device utilizes selective precharge and charge sharing to reduce a bit line voltage before accessing a bit cell (34). A reduction in bit line voltage is achieved by precharging different sections (31, 33) of the bit line to different voltages (e.g., a supply voltage and ground) and using charge sharing between these sections. Read stability improves as a result of the reduction of bit line voltage. The relative capacitance difference (B2-C2) between bit line sections determines the bit line voltage after charge sharing. Thus, the memory device is tolerant to process or temperature variations. The bit line voltage may be controlled in design by selecting the sections that are precharged to supply voltage or ground.
摘要翻译：存储器件利用选择性预充电和电荷共享以在访问位单元（34）之前降低位线电压。通过将位线的不同部分（31,33）预充电到不同的电压（例如，电源电压和接地）并且使用这些部分之间的电荷共享来实现位线电压的降低。读取稳定性由于位线电压的降低而得到改善。位线部分之间的相对电容差（B2-C2）决定电荷共享后的位线电压。因此，存储器件容忍处理或温度变化。可以通过选择预充电以供应电压或接地的部分来设计位线电压。

2. 发明申请

WO2010027915A2 CMOS LEVEL SHIFTER CIRCUIT DESIGN 审中-公开
标题翻译： CMOS水平更换电路设计
公开(公告)号：WO2010027915A2
公开(公告)日：2010-03-11
申请号：PCT/US2009/055339
申请日：2009-08-28
申请人： QUALCOMM Incorporated , CHABA, Ritu , PARK, Dongkyu , JUNG, ChangHo , YOON, Sei Seung
发明人： CHABA, Ritu , PARK, Dongkyu , JUNG, ChangHo , YOON, Sei Seung
IPC分类号： H03K3/356 , H03K3/012
CPC分类号： H03K3/356113 , H03K3/012 , H03K3/356182
摘要： A level shifting circuit has a pair of assist circuits. The level shifting circuit includes an input point, an output point, a pair of cross-coupled PMOS transistors coupled to the output point, and a pair of NMOS transistors coupled between the input and output points. Each assist circuit includes a pair of PMOS transistors, one responsive to an input applied to the input point, the other responsive to the drain voltage of one of the NMOS transistors. The assist circuits temporarily weaken the cross-coupled PMOS transistors when an input changes from low to high, or from high to low. The assist circuits also transiently boost the output.
摘要翻译：电平移位电路具有一对辅助电路。电平移位电路包括耦合到输出点的输入点，输出点，一对交叉耦合PMOS晶体管和耦合在输入和输出点之间的一对NMOS晶体管。每个辅助电路包括一对响应于输入点的输入的PMOS晶体管，另一个响应于NMOS晶体管之一的漏极电压。当输入从低电平变为高电平或从高电平变为低电平时，辅助电路暂时弱化交叉耦合的PMOS晶体管。辅助电路也暂时提升输出。

3. 发明申请

WO2012040375A1 REGISTERS WITH FULL SCAN CAPABILITY 审中-公开
标题翻译：具有全扫描能力的注册
公开(公告)号：WO2012040375A1
公开(公告)日：2012-03-29
申请号：PCT/US2011/052629
申请日：2011-09-21
申请人： QUALCOMM Incorporated , RAO, Hari M. , YOON, Sei Seung , CHEN, Nan
发明人： RAO, Hari M. , YOON, Sei Seung , CHEN, Nan
IPC分类号： G11C29/32 , G01R31/3185
CPC分类号： G01R31/318541 , G11C11/417 , G11C29/32
摘要： A scan test of a first latch and a second latch couples a given scan value to the input of the first latch, to switch the first latch to a state corresponding to the scan value, uncouples the scan value from the first latch to latch the first latch at that state, couples the output of the first latch while latched at that state to the input of the second latch to switch the second latch to that state, and uncoupling the output of the first latch from the input of the second latch to latch the second latch at that state.
摘要翻译：第一锁存器和第二锁存器的扫描测试将给定扫描值耦合到第一锁存器的输入，以将第一锁存器切换到与扫描值对应的状态，将扫描值从第一锁存器解耦合以锁定第一锁存器在该状态下锁存，将锁定在该状态的第一锁存器的输出耦合到第二锁存器的输入，以将第二锁存器切换到该状态，以及将第一锁存器的输出与第二锁存器的输入端分离在该状态下的第二个闩锁。

4. 发明申请

WO2010111394A2 SELF-TIMING FOR A MULTI-PORTED MEMORY SYSTEM 审中-公开
标题翻译：多时间存储器系统的自适应
公开(公告)号：WO2010111394A2
公开(公告)日：2010-09-30
申请号：PCT/US2010/028508
申请日：2010-03-24
申请人： QUALCOMM INCORPORATED , RAO, Hari , JUNG, Chang Ho , CHEN, Nan , YOON, Sei Seung
发明人： RAO, Hari , JUNG, Chang Ho , CHEN, Nan , YOON, Sei Seung
IPC分类号： G06F13/16 , G06F12/00 , G06F1/04
CPC分类号： G11C7/1075 , G11C7/22 , G11C7/227 , G11C2207/007
摘要： Multi-ported memory systems (e.g., register files) employ self-timing for operational synchronization. Thus, rather than using a reference clock duty cycle for operational synchronization, as in conventional multi-ported register files, embodiments of the present disclosure employ self-timing for such operational synchronization. According to certain embodiments, self-timing is employed to synchronize all the internal events within the memory so that all the events are spaced in time for appropriate synchronization. For instance, the completion of one event leads to triggering another event, the completion of which leads to triggering another event, and so on. Thus, in one embodiment, the self-timing is achieved by referencing the operational events with the memory (or register file) to each other, rather than to a reference clock duty cycle.
摘要翻译：多端口存储器系统（例如，寄存器文件）采用用于操作同步的自定时。因此，如在传统的多端口寄存器文件中那样，不像使用用于操作同步的参考时钟占空比，本公开的实施例采用用于这种操作同步的自定时。根据某些实施例，采用自定时来同步存储器内的所有内部事件，使得所有事件在时间上被间隔开以进行适当的同步。例如，一个事件的完成导致触发另一个事件，其完成导致触发另一个事件，等等。因此，在一个实施例中，通过将存储器（或寄存器文件）的操作事件引用到彼此而不是参考时钟占空比来实现自定时。

5. 发明申请

WO2008109768A1 WORD LINE TRANSISTOR STRENGTH CONTROL FOR READ AND WRITE IN SPIN TRANSFER TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY 审中-公开
标题翻译：用于读和写转子转移转矩磁极随机存取存储器的字线晶体管强度控制
公开(公告)号：WO2008109768A1
公开(公告)日：2008-09-12
申请号：PCT/US2008/056086
申请日：2008-03-06
申请人： QUALCOMM INCORPORATED , YOON, Sei Seung , KANG, Seung H. , SANI, Mehdi Hamidi
发明人： YOON, Sei Seung , KANG, Seung H. , SANI, Mehdi Hamidi
IPC分类号： G11C11/16
CPC分类号： G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： Systems, circuits and methods for controlling word line voltage at a word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT- MRAM) are disclosed. A first voltage can be supplied to the word line transistor for write operations. A second voltage, which is less than the first voltage, can be supplied to the word line transistor during read operations.
摘要翻译：公开了用于控制自旋转移磁阻随机存取存储器（STT-MRAM）中的字线晶体管的字线电压的系统，电路和方法。可以向字线晶体管提供第一电压用于写入操作。在读取操作期间，可以将小于第一电压的第二电压提供给字线晶体管。

6. 发明申请

WO2008070611A1 PROCESS VARIATION TOLERANT MEMORY DESIGN 审中-公开
标题翻译：过程变异容错设计
公开(公告)号：WO2008070611A1
公开(公告)日：2008-06-12
申请号：PCT/US2007/086249
申请日：2007-12-03
申请人： QUALCOMM Incorporated , JUNG, Seong-Ook , YOON, Sei Seung , NHO, Hynwoo
发明人： JUNG, Seong-Ook , YOON, Sei Seung , NHO, Hynwoo
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5045 , G06F2217/10
摘要： Methods and systems for designing process variation tolerant memory are disclosed. A memory circuit is divided into functional blocks. A statistical distribution is calculated for each of the functional blocks. Then, the distributions of each block are combined to verify a credibility of the circuit. The credibility is verified if the circuit meets a predetermined yield.
摘要翻译：公开了用于设计过程变化容限存储器的方法和系统。存储电路分为功能块。计算每个功能块的统计分布。然后，组合每个块的分布，以验证电路的可信度。如果电路满足预定的收益率，则验证可信度。

7. 发明申请

WO2010053970A1 WORD LINE VOLTAGE CONTROL IN STT-MRAM 审中-公开
标题翻译： STT-MRAM中的字线电压控制
公开(公告)号：WO2010053970A1
公开(公告)日：2010-05-14
申请号：PCT/US2009/063245
申请日：2009-11-04
申请人： QUALCOMM Incorporated , YOON, Sei Seung , SANI, Mehdi Hamidi , KANG, Seung H.
发明人： YOON, Sei Seung , SANI, Mehdi Hamidi , KANG, Seung H.
IPC分类号： G11C11/16
CPC分类号： G11C8/08 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： Systems, circuits and methods for controlling the word line voltage applied to word line transistors (410) in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ, 405) and a word line transistor. The bit cell is coupled to a bit line (420) and a source line (440). A word line driver (432) is coupled to a gate of the word line transistor. The word line driver is configured to provide a word line voltage greater than a supply voltage below "a transition voltage of the supply voltage and to provide a voltage less than the supply voltage for supply voltages above the transition voltage.
摘要翻译：公开了用于控制施加到自旋转移磁阻随机存取存储器（STT-MRAM）中的字线晶体管（410）的字线电压的系统，电路和方法。一个实施例涉及包括具有磁性隧道结（MTJ，405）和字线晶体管的位单元的STT-MRAM。位单元耦合到位线（420）和源极线（440）。字线驱动器（432）耦合到字线晶体管的栅极。字线驱动器被配置为提供大于低于“电源电压的转换电压”的电源电压的字线电压，并且为电压高于转换电压提供小于电源电压的电压。

8. 发明申请

WO2008109772A1 READ DISTURB REDUCTION CIRCUIT FOR SPIN TRANSFER TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY 审中-公开
标题翻译：读取干扰转移磁阻随机存取存储器的干扰减少电路
公开(公告)号：WO2008109772A1
公开(公告)日：2008-09-12
申请号：PCT/US2008/056090
申请日：2008-03-06
申请人： QUALCOMM INCORPORATED , YOON, Sei Seung , KANG, Seung H. , SANI, Mehdi Hamidi
发明人： YOON, Sei Seung , KANG, Seung H. , SANI, Mehdi Hamidi
IPC分类号： G11C7/06 , G11C11/16
CPC分类号： G11C7/02 , G11C7/062 , G11C7/067 , G11C7/12 , G11C11/1673
摘要： Systems, circuits and methods for reducing read disturbances in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A resistive element can be used during the read operation to control the read current and control read disturbances. An isolation element can be used to isolate the resistive element from the circuit during write operations.
摘要翻译：公开了用于减小转移转矩磁阻随机存取存储器（STT-MRAM）中的读取干扰的系统，电路和方法。在读取操作期间可以使用电阻元件来控制读取电流和控制读取干扰。隔离元件可用于在写入操作期间将电阻元件与电路隔离。

9. 发明申请

WO2010077611A1 DIGITALLY-CONTROLLABLE DELAY FOR SENSE AMPLIFIER 审中-公开
标题翻译：用于感应放大器的数字控制延时
公开(公告)号：WO2010077611A1
公开(公告)日：2010-07-08
申请号：PCT/US2009/066999
申请日：2009-12-07
申请人： QUALCOMM INCORPORATED , PARK, Dongkyu , DAVIERWALLA, Anosh B. , ZHONG, Cheng , ABU-RAHMA, Mohamed Hassan Soliman , YOON, Sei Seung
发明人： PARK, Dongkyu , DAVIERWALLA, Anosh B. , ZHONG, Cheng , ABU-RAHMA, Mohamed Hassan Soliman , YOON, Sei Seung
IPC分类号： G11C7/06 , G11C7/22 , G11C11/16
CPC分类号： G11C7/22 , G11C7/06 , G11C11/1673 , G11C11/1693 , G11C2207/065 , G11C2207/2281
摘要： Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. A circuit includes a sense amplifier (160), having a first input (162), a second input (164), and an enable input (166); a first amplifier (132) coupled to an output of a magnetic resistance-based memory cell (112); a second amplifier (134) coupled to a reference output of the cell; and a digitally-controllable amplifier (136) coupled to a tracking circuit cell (116) that is similar to the cell of the MRAM. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit (150). The sense amplifier may generate an output value based on the amplified values received from the output of the magnetic resistance-based memory cell and the reference cell once the sense amplifier receives an enable signal (152) from the digitally-controllable amplifier via the logic circuit.
摘要翻译：公开了在读取磁随机存取存储器（MRAM）装置中插入可选延迟的电路，装置和方法。电路包括具有第一输入（162），第二输入（164）和使能输入（166）的读出放大器（160）。耦合到基于磁阻的存储单元（112）的输出端的第一放大器（132）; 耦合到所述单元的参考输出的第二放大器（134）以及耦合到类似于MRAM的单元的跟踪电路单元（116）的数字可控放大器（136）。读出放大器的第一输入耦合到第一放大器，读出放大器的第二输入耦合到第二放大器，而使能输入经由逻辑电路（150）耦合到第三数字可控放大器。一旦感测放大器从数字可控放大器经由逻辑电路接收到使能信号（152），读出放大器可以基于从基于磁阻的存储单元和参考单元的输出接收的放大值来产生输出值。

10. 发明申请

WO2010053955A1 DATA PROTECTION DURING POWER-UP IN SPIN TRANSFER TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY 审中-公开
标题翻译：旋转传动扭矩过程中的数据保护磁阻随机访问存储器
公开(公告)号：WO2010053955A1
公开(公告)日：2010-05-14
申请号：PCT/US2009/063225
申请日：2009-11-04
申请人： QUALCOMM Incorporated , YOON, Sei Seung , KANG, Seung H.
发明人： YOON, Sei Seung , KANG, Seung H.
IPC分类号： G11C11/16
CPC分类号： G11C8/08 , G11C7/20 , G11C11/1653 , G11C11/1659 , G11C11/1675
摘要： A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) array including a plurality of bit cells (420-432), a power-up controller (405), and a first plurality of precharge transistors (410-413) is disclosed. The plurality of bit cells are each coupled to one of a plurality of bit lines (BL) and word lines (WL). The power-up controller is configured to provide a power-up control signal to control the voltage level of at least one of the bit lines or the word lines during power-up. The first plurality of precharge transistors are respectively coupled to at least one of the plurality of bit lines or the plurality of word lines, each precharge transistor being configured to discharge a corresponding bit line or word line to a desired voltage level based on the power-up control signal.
摘要翻译：公开了包括多个位单元（420-432），上电控制器（405）和第一多个预充电晶体管（410-413）的自旋转移力矩磁阻随机存取存储器（STT-MRAM）阵列。多个比特单元各自耦合到多个位线（BL）和字线（WL）中的一个。上电控制器被配置为提供上电控制信号以在上电期间控制至少一个位线或字线的电压电平。第一多个预充电晶体管分别耦合到多个位线或多个字线中的至少一个，每个预充电晶体管被配置为基于功率放大晶体管将相应的位线或字线放电到期望的电压电平，控制信号。

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